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[84.20.244.219]) by smtp.gmail.com with ESMTPSA id y9sm23062787wmj.36.2021.09.20.06.26.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 06:26:01 -0700 (PDT) From: Krzysztof Kozlowski To: Rob Herring , Paul Walmsley , Palmer Dabbelt , Albert Ou , Krzysztof Kozlowski , Geert Uytterhoeven , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RESEND PATCH] dt-bindings: riscv: correct e51 and u54-mc CPU bindings Date: Mon, 20 Sep 2021 15:25:59 +0200 Message-Id: <20210920132559.151678-1-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210920_062604_334974_4014F347 X-CRM114-Status: GOOD ( 12.15 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org All existing boards with sifive,e51 and sifive,u54-mc use it on top of sifive,rocket0 compatible: arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: cpu@0: compatible: 'oneOf' conditional failed, one must be fixed: ['sifive,e51', 'sifive,rocket0', 'riscv'] is too long Additional items are not allowed ('riscv' was unexpected) Additional items are not allowed ('sifive,rocket0', 'riscv' were unexpected) 'riscv' was expected Signed-off-by: Krzysztof Kozlowski --- Hi Rob, You previously acked this patch but I think it will be easier if you take it directly. Best regards, Krzysztof --- Documentation/devicetree/bindings/riscv/cpus.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index e534f6a7cfa1..aa5fb64d57eb 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -31,9 +31,7 @@ properties: - sifive,bullet0 - sifive,e5 - sifive,e7 - - sifive,e51 - sifive,e71 - - sifive,u54-mc - sifive,u74-mc - sifive,u54 - sifive,u74 @@ -41,6 +39,12 @@ properties: - sifive,u7 - canaan,k210 - const: riscv + - items: + - enum: + - sifive,e51 + - sifive,u54-mc + - const: sifive,rocket0 + - const: riscv - const: riscv # Simulator only description: Identifies that the hart uses the RISC-V instruction set