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[84.20.244.219]) by smtp.gmail.com with ESMTPSA id g1sm45429wmk.2.2021.09.20.06.28.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 06:28:42 -0700 (PDT) From: Krzysztof Kozlowski To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Paul Walmsley , Palmer Dabbelt , Albert Ou , Krzysztof Kozlowski , Geert Uytterhoeven , Conor Dooley , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v2 5/5] riscv: dts: microchip: use vendor compatible for Cadence SD4HC Date: Mon, 20 Sep 2021 15:28:30 +0200 Message-Id: <20210920132830.152802-5-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210920132830.152802-1-krzysztof.kozlowski@canonical.com> References: <20210920132830.152802-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210920_062844_546674_E963ACE4 X-CRM114-Status: GOOD ( 12.33 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Licensed IP blocks should have their own vendor compatible. Signed-off-by: Krzysztof Kozlowski --- Changes since v1: 1. New patch --- arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index 55d86b078c53..7948c4249de5 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -263,7 +263,7 @@ serial3: serial@20104000 { }; mmc: mmc@20008000 { - compatible = "cdns,sd4hc"; + compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc"; reg = <0x0 0x20008000 0x0 0x1000>; interrupt-parent = <&plic>; interrupts = <88>;