From patchwork Thu Oct 21 17:42:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emil Renner Berthing X-Patchwork-Id: 12575947 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B37A1C433F5 for ; Thu, 21 Oct 2021 17:43:24 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A33456112D for ; Thu, 21 Oct 2021 17:43:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org A33456112D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=esmil.dk Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=fjcUqh9tZu/bfdZodORw5KrLSHL7+50Nlqd458vxSKc=; b=RSNQzKjxi77iR/ bpNxgC955E6uStaKgGo/W+331NZ4xQ0V+5RlykOvLSwqlpyxBYAInlTtrB7VC5tNNQzMY3h6Fl/rV Sk43i/r2O/mFlNMHK7FNmEg642rpUPkaLvjeyg/E9yX5rcT1953FsOGAXnmhEgjAcTqHwd/dW0xHl o8y2eU95q/6XJHEbympF8c8+2y/729msnnUu7IXzenhcUzxskCG5YoipKofCDdoTlJERJwemChRGG XIR+N9SDORH3Da1Eh2H5rQF1+cXLkr704XjX77K8fDRH3AjSI8P8JVWb71C6YwAXQi8VVaGS5jcQa 1p/fjdc+vlpxZutXYP8A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mdc5z-008We9-Tr; Thu, 21 Oct 2021 17:43:15 +0000 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mdc5X-008WGl-Vb for linux-riscv@lists.infradead.org; Thu, 21 Oct 2021 17:42:50 +0000 Received: by mail-ed1-x534.google.com with SMTP id w14so4151270edv.11 for ; Thu, 21 Oct 2021 10:42:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=etaQItRNjj/enFUFDfmsaC1oEhl7tTCegAPe8SqnEa4=; b=eIVkPoB3xWsbjt8wgQz73InY7RH6tRQRCDu7Ulm3xncO1vsHfjLwzLozB0fFeiGBA9 x3y24NKBXtFYw1dMJAnWDKkn2eqf81+XiiVMomxLIyM47wGjiExqCcYURsYpIdZruHG5 qOQR+DTAjT4TGSdsDlvNzMVP03fbTvpYYLld6PwrRx0UhRyUDcfNDXDJJpshWZFxlTS6 No/JOuQnJ4okkX3ZejdvOAWl8m15jK+iPXX+eILFUGuoyazDUXfp9cJsbej1hBr68ZWq vtyf3iTVC4ohJrvBxcQE7iW+XVJrcHIXAK8oJbMB6n8I3mJoVFnZol5eq3Jl/+w1yDFC GQcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=etaQItRNjj/enFUFDfmsaC1oEhl7tTCegAPe8SqnEa4=; b=UIXwnWRbw9QlDS0NULFxZCQ4474Z/4IBZvaMf0aDL4zEcTcI/OCbdiUVl2pSeBpnGr HvY5JtyLN7o5Q1UySbxXeMzVla23kegJ7gmsc2XxwfPh2LqUPZKB7i3CZzRMVDH/93WV k6WgU61Tq/aA8izo6rtW60HpCKkyXbZ91HPmyWZfgajVXQDma8piPCYlGD1CGvu8J5SW zoAcEDcJq75r4D5polZPG3I/uziiFLa/r6E4I9F48x9eQwCRFKRPi9gfUqsih3M2dO2b NTZ9HYo6NVpKpHaRK8dQV1r+wdGYmMxUsoRH5kdLwsFvUVYN4Si0u4Noq4F6eK9zAdYp y6MQ== X-Gm-Message-State: AOAM532kG4KcKrDiftO6oBUrUazsoBK9T9krFhQlpYPkBJPI1ASjYIJf B94hpcgloyj++MOUPaNRmOiKP7+1iKIqqg== X-Google-Smtp-Source: ABdhPJwVll2mJspTJ9A4kA87pSHYnhNxbDLsRGZEBnQWv+H7059RHoYerbJmgK3bsHbA9nhbHCzhOg== X-Received: by 2002:a05:6402:4304:: with SMTP id m4mr9575901edc.326.1634838166756; Thu, 21 Oct 2021 10:42:46 -0700 (PDT) Received: from stitch.. (80.71.140.73.ipv4.parknet.dk. [80.71.140.73]) by smtp.gmail.com with ESMTPSA id h7sm3144847edt.37.2021.10.21.10.42.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Oct 2021 10:42:46 -0700 (PDT) From: Emil Renner Berthing To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org Cc: Emil Renner Berthing , Palmer Dabbelt , Paul Walmsley , Rob Herring , Michael Turquette , Stephen Boyd , Thomas Gleixner , Marc Zyngier , Philipp Zabel , Linus Walleij , Greg Kroah-Hartman , Daniel Lezcano , Andy Shevchenko , Jiri Slaby , Maximilian Luz , Sagar Kadam , Drew Fustini , Geert Uytterhoeven , Michael Zhu , Fu Wei , Anup Patel , Atish Patra , Matteo Croce , linux-kernel@vger.kernel.org Subject: [PATCH v2 11/16] dt-bindings: pinctrl: Add StarFive JH7100 bindings Date: Thu, 21 Oct 2021 19:42:18 +0200 Message-Id: <20211021174223.43310-12-kernel@esmil.dk> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211021174223.43310-1-kernel@esmil.dk> References: <20211021174223.43310-1-kernel@esmil.dk> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211021_104248_107391_240B6C18 X-CRM114-Status: GOOD ( 18.99 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add bindings for the StarFive JH7100 GPIO/pin controller. Signed-off-by: Emil Renner Berthing --- .../pinctrl/starfive,jh7100-pinctrl.yaml | 274 ++++++++++++++++++ 1 file changed, 274 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml new file mode 100644 index 000000000000..342ecd91a3b0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml @@ -0,0 +1,274 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7100 Pin Controller Device Tree Bindings + +maintainers: + - Emil Renner Berthing + - Drew Fustini + +properties: + compatible: + const: starfive,jh7100-pinctrl + + reg: + minItems: 2 + maxItems: 2 + + reg-names: + items: + - const: "gpio" + - const: "padctl" + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: | + Number of cells in GPIO specifier. Since the generic GPIO + binding is used, the amount of cells must be specified as 2. + + interrupts: + maxItems: 1 + description: The GPIO parent interrupt. + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + starfive,signal-group: + description: | + The SoC has a global setting selecting one of 7 different pinmux + configurations of the pads named GPIO[0:63] and FUNC_SHARE[0:141]. After + this global setting is chosen only the 64 "GPIO" pins can be further + muxed by configuring them to be controlled by certain peripherals rather + than software. + Note that in configuration 0 none of GPIOs are routed to pads, and only + in configuration 1 are the GPIOs routed to the pads named GPIO[0:63]. + If this property is not set it defaults to the configuration already + chosen by the earlier boot stages. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6] + +required: + - compatible + - reg + - reg-names + - clocks + - gpio-controller + - "#gpio-cells" + - interrupts + - interrupt-controller + - "#interrupt-cells" + +patternProperties: + '-[0-9]*$': + type: object + patternProperties: + '-pins*$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to + muxer configuration, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate and drive strength. + $ref: "/schemas/pinctrl/pincfg-node.yaml" + + properties: + pins: + description: | + The list of pin identifiers that properties in the node apply to. + This should be set using either the PAD_GPIO or PAD_FUNC_SHARE + macro. Either this or "pinmux" has to be specified. + + pinmux: + description: | + The list of GPIO identifiers and their mux settings that + properties in the node apply to. This should be set using the + GPIOMUX macro. Either this or "pins" has to be specified. + + bias-disable: true + + bias-pull-up: + type: boolean + + bias-pull-down: + type: boolean + + drive-strength: + enum: [ 14, 21, 28, 35, 42, 49, 56, 63 ] + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + maximum: 7 + + starfive,strong-pull-up: + description: enable strong pull-up. + type: boolean + + additionalProperties: false + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + gpio: pinctrl@11910000 { + compatible = "starfive,jh7100-pinctrl"; + reg = <0x0 0x11910000 0x0 0x10000>, + <0x0 0x11858000 0x0 0x1000>; + reg-names = "gpio", "padctl"; + clocks = <&clkgen JH7100_CLK_GPIO_APB>; + resets = <&clkgen JH7100_RSTN_GPIO_APB>; + interrupts = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + starfive,signal-group = <6>; + + gmac_pins_default: gmac-0 { + gtxclk-pins { + pins = ; + bias-pull-up; + drive-strength = <35>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + miitxclk-pins { + pins = ; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + tx-pins { + pins = , + , + , + , + , + , + , + , + ; + bias-disable; + drive-strength = <35>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + rxclk-pins { + pins = ; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-disable; + slew-rate = <6>; + }; + rxer-pins { + pins = ; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + rx-pins { + pins = , + , + , + , + , + , + , + , + , + , + , + , + ; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + + i2c0_pins_default: i2c0-0 { + i2c-pins { + pinmux = , + ; + bias-disable; /* external pull-up */ + input-enable; + input-schmitt-enable; + }; + }; + + uart3_pins_default: uart3-0 { + rx-pin { + pinmux = ; + bias-pull-up; + input-enable; + input-schmitt-enable; + }; + tx-pin { + pinmux = ; + bias-disable; + input-disable; + input-schmitt-disable; + }; + }; + }; + + gmac { + pinctrl-0 = <&gmac_pins_default>; + pinctrl-names = "default"; + }; + + i2c0 { + pinctrl-0 = <&i2c0_pins_default>; + pinctrl-names = "default"; + }; + + uart3 { + pinctrl-0 = <&uart3_pins_default>; + pinctrl-names = "default"; + }; + }; + +...