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25 Oct 2021 12:29:28 -0700 IronPort-SDR: jLN67SRVfQ+M8+lWYHBkvJyusCdkYeJWN08Daox/eGpo/VDrAkxVzvwHTwfCybR8nuR/tZYPp4 JmJgABWCz0xAZOxey6qHU60t+vG1WzHC0+21yiIs/mAmmYDnjpmSpez70Ut0VqG1uQ8yImW6bb YKLAHOzXWu5cxqZ46dXPImaNjoKNoKf5AKz7P1w0+ybJ1/Ym9X6xcEh+BSI1Ho42yBcGUwTw6u psiG/vsL370mzCaA9PsABoDg/AbKi+IYRi3OlnRCsp4jupTcQcNdMMqEDFJBbM/28MXbT3dJfv zFM= WDCIronportException: Internal Received: from unknown (HELO hulk.wdc.com) ([10.225.167.27]) by uls-op-cesaip01.wdc.com with ESMTP; 25 Oct 2021 12:53:58 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , David Abdurachmanov , devicetree@vger.kernel.org, Greentime Hu , Guo Ren , Heinrich Schuchardt , Jonathan Corbet , linux-doc@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, Nick Kossifidis , Palmer Dabbelt , Paul Walmsley , Rob Herring , Vincent Chen Subject: [v4 06/11] dt-binding: pmu: Add RISC-V PMU DT bindings Date: Mon, 25 Oct 2021 12:53:45 -0700 Message-Id: <20211025195350.242914-7-atish.patra@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211025195350.242914-1-atish.patra@wdc.com> References: <20211025195350.242914-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211025_125401_179757_989A2709 X-CRM114-Status: GOOD ( 13.69 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This patch adds the DT bindings for RISC-V PMU driver. It also defines the interrupt related properties to allow counter overflow interrupt. Signed-off-by: Atish Patra --- .../devicetree/bindings/perf/riscv,pmu.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/perf/riscv,pmu.yaml diff --git a/Documentation/devicetree/bindings/perf/riscv,pmu.yaml b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml new file mode 100644 index 000000000000..497caad63f16 --- /dev/null +++ b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pmu/riscv,pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V PMU + +maintainers: + - Atish Patra + +description: + The "Sscofpmf" extension allows the RISC-V PMU counters to overflow and + generate a local interrupt so that event sampling can be done from user-space. + The above said ISA extension is an optional extension to maintain backward + compatibility and will be included in privilege specification v1.12 . That's + why the interrupt property is marked as optional. The platforms with sscofpmf + extension should add this property to enable event sampling. + The device tree node with the compatible string is mandatory for any platform + that wants to use pmu counter start/stop methods using SBI PMU extension. + +properties: + compatible: + enum: + - riscv,pmu + + description: + Should be "riscv,pmu". + + interrupts-extended: + minItems: 1 + maxItems: 4095 + +additionalProperties: false + +required: + - None +optional: + - compatible + - interrupts-extended + +examples: + - | + pmu { + compatible = "riscv,pmu"; + interrupts-extended = <&cpu0intc 13>, + <&cpu1intc 13>, + <&cpu2intc 13>, + <&cpu3intc 13>; + }; +...