| Message ID | 20220120153338.4093003-2-gatecat@ds0.me (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: Fixes for XIP support | expand |
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 604d60292dd8..b1ca65abeb1e 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -21,14 +21,13 @@ add \reg, \reg, t0 .endm .macro XIP_FIXUP_FLASH_OFFSET reg - la t1, __data_loc - li t0, XIP_OFFSET_MASK - and t1, t1, t0 - li t1, XIP_OFFSET - sub t0, t0, t1 - sub \reg, \reg, t0 + la t0, __data_loc + REG_L t1, _xip_phys_offset + sub \reg, \reg, t1 + add \reg, \reg, t0 .endm _xip_fixup: .dword CONFIG_PHYS_RAM_BASE - CONFIG_XIP_PHYS_ADDR - XIP_OFFSET +_xip_phys_offset: .dword CONFIG_XIP_PHYS_ADDR + XIP_OFFSET #else .macro XIP_FIXUP_OFFSET reg .endm
There were several problems with the calculation. Not only was an 'and' being computed into t1 but thrown away; but the 'and' itself would cause problems if the granularity of the XIP physical address was less than XIP_OFFSET - in my case I had the kernel image at 2MB in SPI flash. I believe this approach is more generic. Fixes: f9ace4ede49b ("riscv: remove .text section size limitation for XIP") Signed-off-by: Myrtle Shah <gatecat@ds0.me> --- arch/riscv/kernel/head.S | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-)