From patchwork Fri Jan 21 16:36:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 12719921 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 51579C4332F for ; Fri, 21 Jan 2022 16:37:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=BnSamubChpor/K4vouK/jIt3PiDXUVEkpW0nhF5hbXA=; b=FDndaIYgrzvZtK uzT6DUffnPioRq/LmlbLG4n9fCp4AOcgfcYwb6ufy4ibBoN2MzfVmwLlQxNUW7eQ1n4Ti2SedA4mD GDmG9AgExm3tZfNMdtgWiQwJf6l7FEhyu4E24dZKlUI6Pj8Y0nemTMTvWBhhI6BhTaVmWT8mxA7we Wm2WxK3Iiy2j1Avrez1zhdOEghmud0y6C6CFlOendZl5hxIVSR9sAvnAeXGjAFCVwVdkHAudF7kPm f3ANCqDetXtdZe7dNc8+7qQxA7HUbo9SjEQCyPdcUvVmEK+3oRoDLzTkr81kUF/oNHAbqhzCiceTL kNjHd9MF0yahThGqVv9g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nAwui-00FZci-MP; Fri, 21 Jan 2022 16:37:24 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nAwuZ-00FZXg-Pj for linux-riscv@bombadil.infradead.org; Fri, 21 Jan 2022 16:37:15 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:MIME-Version :References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=AZ3BEKK1NUFHQjnYeUn/gpzCXgeOnYmofu2OKhIJz1U=; b=pV3xco+s2Kbf2OqYEzf2P72FqN GvIhpd5vhkOJlzBvQyhXoRa9gkJQ5DagsDJwAqiAq0Vr45CV9MndpDUAUDHJDbt6GtelpTxJR/Ij4 zSzeZf20zgEOBfR4wABLcncJaMhiWwzojKvDrSZ/k9p7QCEq5jGqwfZmgy61kKcg2JLQhruS9iciS 7wPA0EGyuym15ubueW/yYqthupW4u15YjyWGUdNxC8rQejn+qIfFWQevDGDYDAH6e1cm5C+8S+ipD 6Pmjc+rM56QvY4Gcn71GHKFFXC1uyDYObh+eRKE6xz1Fh28uNN4UD5/djcik5ovfG8R1DWJuZR5eA HEIj5Gog==; Received: from gloria.sntech.de ([185.11.138.130]) by desiato.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nAwuW-002bxf-Cg for linux-riscv@lists.infradead.org; Fri, 21 Jan 2022 16:37:14 +0000 Received: from p508fcef5.dip0.t-ipconnect.de ([80.143.206.245] helo=phil.fritz.box) by gloria.sntech.de with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nAwuG-0008GA-M9; Fri, 21 Jan 2022 17:36:56 +0100 From: Heiko Stuebner To: palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, wefu@redhat.com, liush@allwinnertech.com, guoren@kernel.org, atishp@atishpatra.org, anup@brainfault.org, drew@beagleboard.org, hch@lst.de, arnd@arndb.de, wens@csie.org, maxime@cerno.tech, dlustig@nvidia.com, gfavor@ventanamicro.com, andrea.mondelli@huawei.com, behrensj@mit.edu, xinhaoqu@huawei.com, huffman@cadence.com, mick@ics.forth.gr, allen.baum@esperantotech.com, jscheid@ventanamicro.com, rtrauben@gmail.com, samuel@sholland.org, cmuellner@linux.com, philipp.tomsich@vrull.eu, Heiko Stuebner Subject: [PATCH v5 02/14] riscv: integrate alternatives better into the main architecture Date: Fri, 21 Jan 2022 17:36:06 +0100 Message-Id: <20220121163618.351934-3-heiko@sntech.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220121163618.351934-1-heiko@sntech.de> References: <20220121163618.351934-1-heiko@sntech.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220121_163712_558147_3BF219D8 X-CRM114-Status: GOOD ( 16.92 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Right now the alternatives need to be explicitly enabled and erratas are limited to SiFive ones. Over time with more SoCs and additional RiscV extensions, many more erratas or other patch-worthy features will emerge, so it doesn't really make sense to have the core alternatives able to get deactivated. So make it part of the core RiscV kernel and drop the main RISCV_ERRATA_ALTERNATIVES config symbol. This also mimics how arm64 handles its alternatives implementation. Signed-off-by: Heiko Stuebner --- arch/riscv/Kconfig.erratas | 10 ---------- arch/riscv/Kconfig.socs | 1 - arch/riscv/Makefile | 2 +- arch/riscv/errata/Makefile | 1 - arch/riscv/include/asm/alternative-macros.h | 22 --------------------- arch/riscv/kernel/Makefile | 1 + arch/riscv/{errata => kernel}/alternative.c | 0 arch/riscv/kernel/smpboot.c | 2 -- arch/riscv/kernel/traps.c | 2 +- 9 files changed, 3 insertions(+), 38 deletions(-) rename arch/riscv/{errata => kernel}/alternative.c (100%) diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas index b44d6ecdb46e..d18be8ff0245 100644 --- a/arch/riscv/Kconfig.erratas +++ b/arch/riscv/Kconfig.erratas @@ -1,17 +1,7 @@ menu "CPU errata selection" -config RISCV_ERRATA_ALTERNATIVE - bool "RISC-V alternative scheme" - default y - help - This Kconfig allows the kernel to automatically patch the - errata required by the execution platform at run time. The - code patching is performed once in the boot stages. It means - that the overhead from this mechanism is just taken once. - config ERRATA_SIFIVE bool "SiFive errata" - depends on RISCV_ERRATA_ALTERNATIVE help All SiFive errata Kconfig depend on this Kconfig. Disabling this Kconfig will disable all SiFive errata. Please say "Y" diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 6ec44a22278a..3df7f7ed0d81 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -14,7 +14,6 @@ config SOC_SIFIVE select CLK_SIFIVE select CLK_SIFIVE_PRCI select SIFIVE_PLIC - select RISCV_ERRATA_ALTERNATIVE select ERRATA_SIFIVE help This enables support for SiFive SoC platform hardware. diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 8a107ed18b0d..194220889969 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -97,7 +97,7 @@ endif head-y := arch/riscv/kernel/head.o -core-$(CONFIG_RISCV_ERRATA_ALTERNATIVE) += arch/riscv/errata/ +core-y += arch/riscv/errata/ core-$(CONFIG_KVM) += arch/riscv/kvm/ libs-y += arch/riscv/lib/ diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile index b8f8740a3e44..0ca1c5281a2d 100644 --- a/arch/riscv/errata/Makefile +++ b/arch/riscv/errata/Makefile @@ -1,2 +1 @@ -obj-y += alternative.o obj-$(CONFIG_ERRATA_SIFIVE) += sifive/ diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h index 67406c376389..92da6b3920a3 100644 --- a/arch/riscv/include/asm/alternative-macros.h +++ b/arch/riscv/include/asm/alternative-macros.h @@ -2,8 +2,6 @@ #ifndef __ASM_ALTERNATIVE_MACROS_H #define __ASM_ALTERNATIVE_MACROS_H -#ifdef CONFIG_RISCV_ERRATA_ALTERNATIVE - #ifdef __ASSEMBLY__ .macro ALT_ENTRY oldptr newptr vendor_id errata_id new_len @@ -76,26 +74,6 @@ #endif /* __ASSEMBLY__ */ -#else /* !CONFIG_RISCV_ERRATA_ALTERNATIVE*/ -#ifdef __ASSEMBLY__ - -.macro __ALTERNATIVE_CFG old_c - \old_c -.endm - -#define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \ - __ALTERNATIVE_CFG old_c - -#else /* !__ASSEMBLY__ */ - -#define __ALTERNATIVE_CFG(old_c) \ - old_c "\n" - -#define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \ - __ALTERNATIVE_CFG(old_c) - -#endif /* __ASSEMBLY__ */ -#endif /* CONFIG_RISCV_ERRATA_ALTERNATIVE */ /* * Usage: * ALTERNATIVE(old_content, new_content, vendor_id, errata_id, CONFIG_k) diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index fb63b462ff85..62d6860af574 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -18,6 +18,7 @@ extra-y += head.o extra-y += vmlinux.lds obj-y += soc.o +obj-y += alternative.o obj-y += cpu.o obj-y += cpufeature.o obj-y += entry.o diff --git a/arch/riscv/errata/alternative.c b/arch/riscv/kernel/alternative.c similarity index 100% rename from arch/riscv/errata/alternative.c rename to arch/riscv/kernel/alternative.c diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 622f226454d5..a6d13dca1403 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -41,9 +41,7 @@ static DECLARE_COMPLETION(cpu_running); void __init smp_prepare_boot_cpu(void) { init_cpu_topology(); -#ifdef CONFIG_RISCV_ERRATA_ALTERNATIVE apply_boot_alternatives(); -#endif } void __init smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 0daaa3e4630d..18869912d23d 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -86,7 +86,7 @@ static void do_trap_error(struct pt_regs *regs, int signo, int code, } } -#if defined (CONFIG_XIP_KERNEL) && defined (CONFIG_RISCV_ERRATA_ALTERNATIVE) +#if defined (CONFIG_XIP_KERNEL) #define __trap_section __section(".xip.traps") #else #define __trap_section