From patchwork Tue Feb 1 15:05:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 12731886 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0DC1BC433F5 for ; Tue, 1 Feb 2022 15:17:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=E0lyyJ+2PlUEYnrTVe+XluzEJQb+eoNetm61vdz7U2Q=; b=kjucz7RQ/X/sAs E2GEce1HAN9BHQjKBAtgboT84MpxCkdn9gwPeC9+Gaea9+VdiYS4MiEr/z3FyBRST5YPR6uxm+kt+ HbGycCaifuzGHWjrUUSsTkSC0iAdm1IL5c7rw/Jeq5ir28xYNPqW0cWtar9Tv14k4fuXVMVgHUMCt Ne/Hs2MJMMjkr+Ru36KzOpj/HCstWo+8HQw1rzoE1ZVz1gRgEmfgabTDX+CoECGUgzVWqqvTE10vt DjaewHnhHGgzbZxjW73mWUbsDnzNH0tx5Rf+zbUQDeVTX+ZBeqHBYChRrZsMtntBrbJCbvI46lY/O PCo8Qk4gYSb6rtc94lTA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nEuu3-00CbFx-3O; Tue, 01 Feb 2022 15:17:07 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nEuki-00CWLj-5l; Tue, 01 Feb 2022 15:07:31 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id C8E6FB82E40; Tue, 1 Feb 2022 15:07:26 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 72A4AC340ED; Tue, 1 Feb 2022 15:07:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1643728045; bh=gubBLeOVUNo5+99AzAl7peBszEat/rDlyHt7rNu08Ko=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rT9hiXUomydKrnHkjDW2C7KQEb/rekhoqcjElStqZxnRGXlOmWI3UJBjH4S8PAy8/ YBQ4nED71Abc4EFuJRElrGA4tocONhEa4hn/ZEbt9JtVPARYlsbg7E0rSlT7mQTjJl SJL+x07HYT5b0pDSts0Rz99w9s1sW6dMKogCGEb/S8bSJ7ORcYVBUvdXkw9GHId3Wk b8oaet0/c8zNSpxvWZnx3StpByJhabQYAMHz1JnTF6DAQf7sDs4NS6L9ItDtNanjIv wU1jEp+x+SfBfOED8bvmNT0vbDkyYC9C/lETkE2amItWhJEyCFa7ABSSC6raUU4011 PIuJ7gbxo0HEw== From: guoren@kernel.org To: guoren@kernel.org, palmer@dabbelt.com, arnd@arndb.de, anup@brainfault.org, gregkh@linuxfoundation.org, liush@allwinnertech.com, wefu@redhat.com, drew@beagleboard.org, wangjunqiang@iscas.ac.cn, hch@lst.de Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-csky@vger.kernel.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-parisc@vger.kernel.org, linux-mips@vger.kernel.org, linux-arm-kernel@lists.infradead.org, x86@kernel.org, Guo Ren Subject: [PATCH V5 14/21] riscv: compat: Add elf.h implementation Date: Tue, 1 Feb 2022 23:05:38 +0800 Message-Id: <20220201150545.1512822-15-guoren@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220201150545.1512822-1-guoren@kernel.org> References: <20220201150545.1512822-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220201_070728_575679_DDDBFAD8 X-CRM114-Status: GOOD ( 16.19 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren Implement necessary type and macro for compat elf. See the code comment for detail. Signed-off-by: Guo Ren Signed-off-by: Guo Ren Reviewed-by: Arnd Bergmann --- arch/riscv/include/asm/elf.h | 46 +++++++++++++++++++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h index f53c40026c7a..aee40040917b 100644 --- a/arch/riscv/include/asm/elf.h +++ b/arch/riscv/include/asm/elf.h @@ -8,6 +8,8 @@ #ifndef _ASM_RISCV_ELF_H #define _ASM_RISCV_ELF_H +#include +#include #include #include #include @@ -18,11 +20,13 @@ */ #define ELF_ARCH EM_RISCV +#ifndef ELF_CLASS #ifdef CONFIG_64BIT #define ELF_CLASS ELFCLASS64 #else #define ELF_CLASS ELFCLASS32 #endif +#endif #define ELF_DATA ELFDATA2LSB @@ -31,6 +35,13 @@ */ #define elf_check_arch(x) ((x)->e_machine == EM_RISCV) +/* + * Use the same code with elf_check_arch, because elf32_hdr & + * elf64_hdr e_machine's offset are different. The checker is + * a little bit simple compare to other architectures. + */ +#define compat_elf_check_arch(x) ((x)->e_machine == EM_RISCV) + #define CORE_DUMP_USE_REGSET #define ELF_EXEC_PAGESIZE (PAGE_SIZE) @@ -43,8 +54,14 @@ #define ELF_ET_DYN_BASE ((TASK_SIZE / 3) * 2) #ifdef CONFIG_64BIT +#ifdef CONFIG_COMPAT +#define STACK_RND_MASK (test_thread_flag(TIF_32BIT) ? \ + 0x7ff >> (PAGE_SHIFT - 12) : \ + 0x3ffff >> (PAGE_SHIFT - 12)) +#else #define STACK_RND_MASK (0x3ffff >> (PAGE_SHIFT - 12)) #endif +#endif /* * This yields a mask that user programs can use to figure out what * instruction set this CPU supports. This could be done in user space, @@ -60,11 +77,19 @@ extern unsigned long elf_hwcap; */ #define ELF_PLATFORM (NULL) +#define COMPAT_ELF_PLATFORM (NULL) + #ifdef CONFIG_MMU #define ARCH_DLINFO \ do { \ + /* \ + * Note that we add ulong after elf_addr_t because \ + * casting current->mm->context.vdso triggers a cast \ + * warning of cast from pointer to integer for \ + * COMPAT ELFCLASS32. \ + */ \ NEW_AUX_ENT(AT_SYSINFO_EHDR, \ - (elf_addr_t)current->mm->context.vdso); \ + (elf_addr_t)(ulong)current->mm->context.vdso); \ NEW_AUX_ENT(AT_L1I_CACHESIZE, \ get_cache_size(1, CACHE_TYPE_INST)); \ NEW_AUX_ENT(AT_L1I_CACHEGEOMETRY, \ @@ -90,4 +115,23 @@ do { \ *(struct user_regs_struct *)regs; \ } while (0); +#ifdef CONFIG_COMPAT + +#define SET_PERSONALITY(ex) \ +do { if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \ + set_thread_flag(TIF_32BIT); \ + else \ + clear_thread_flag(TIF_32BIT); \ + if (personality(current->personality) != PER_LINUX32) \ + set_personality(PER_LINUX | \ + (current->personality & (~PER_MASK))); \ +} while (0) + +#define COMPAT_ELF_ET_DYN_BASE ((TASK_SIZE_32 / 3) * 2) + +/* rv32 registers */ +typedef compat_ulong_t compat_elf_greg_t; +typedef compat_elf_greg_t compat_elf_gregset_t[ELF_NGREG]; + +#endif /* CONFIG_COMPAT */ #endif /* _ASM_RISCV_ELF_H */