From patchwork Sun Feb 20 05:08:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12752553 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1CE5DC433EF for ; Sun, 20 Feb 2022 05:10:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=aZbzUQluEkmkWWuumIUTd9d9OPlgIc84l5JYMDhh4K8=; b=CaMxVVWWDSXm5r pU8KGKsVVyDhIylsf0MergsysRgq5UjBT6gRM001/obxlfb/NI8PjyHhAA44VGhEqVHSVElvV8lbO fdgrMKMSWmmWy4wDIjfIxdaBX6h6G/vDa9ZNBmEsH0aU64aM5qGkhTDbJCamS+wAB/CRQBTXN8rSX fk3Xnxz+AA52UmeSueQFekRaXmvrDVBXsZN7ZXlJtPad+1YrvajVFMuL+N6XiNA1SJyNllnVHGRDZ wORlYxqhIGBOr4Mx08e69irVUXsaexFaDBpkDxSd/kctqOCZjYVIuO5a2QwnqF4YyJy32ebALxc2n e2lvbghhTIyrOw2f3q8w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nLeUH-000c66-Qh; Sun, 20 Feb 2022 05:10:21 +0000 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nLeUD-000c2p-To for linux-riscv@lists.infradead.org; Sun, 20 Feb 2022 05:10:19 +0000 Received: by mail-pf1-x42f.google.com with SMTP id x18so5817237pfh.5 for ; Sat, 19 Feb 2022 21:10:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ANfiyTNuLH3K34lM7cYA66sM88G94rOT/TdSDWy1dfM=; b=JF//wm+M5JXxUvJV+hDol5wxtCo/dr6QmP6nGJJr59C+POPrhWYTsExYv94Md/rcst FyA0KcmP0nJ/9MUUBmGG9ivVGVHyFoZE4cX9mSps/3JGn2zevvvrSButE0ZnklortNtH +/Hoc+j3IdIG9fR4Qe4CjGCnqNxnOEfK8BTz9xZRPvs3/2/tEBVeuUqnw+I1PFjnpPmi J0UiY9ih9f89DZJNeWWKuAvI13hj9vYR54GyM4ho+iBlkldpkKvWUaLMoNU01AHaqVhU No6X8xeG3Oiax27NmT5ZmNg0jmdhRZRmJG8Ahv/WuEwnfvGo0AXlpr/EWURLSfkk2vDv 1zlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ANfiyTNuLH3K34lM7cYA66sM88G94rOT/TdSDWy1dfM=; b=XIAmDn3Chz5+bu/beXO3tZTOGZz6BZV9RXn1HWYPlBfgn7vvL18s1EqqLdzW5z0ND/ 2AIAkPJ9RHhLrNcqzDa/9h/mYIGZh0i45NcE1IYC0E6E/q81VejGyv2o01pzvbvM4kMf 8cwId6dhBcSSOSXWCi+yOkILvQx+Trp2jxsb0ZDj/rbdWT5cTE93Qp7bZpTYfIiUFv/a Dp0MUXK+RFZfHOvobv59aArWNFKcF2ktKQXy2n1CuYw/ksdL7QBJg0DSPZFwyCCUW7K9 S7tBlypoFNEJK2BK/dsN9DN8vEyrAlLxTGSJED7/qz4DHyWPhnG1iuGiLF7WEiL4EaLb zZUg== X-Gm-Message-State: AOAM533USMKnSJF5XBrnE2TwLBMsEfvaQ+kyz8JRg54Ne+3PLQrJE7lW LSrEb4RqzLiWspKRLzqGP6U9yQ== X-Google-Smtp-Source: ABdhPJyxhEeATiWoZESJ2C1EqKzR67HpxvZCd6735980MXU+LZNqKX6IJmZEyU1IsZh2JHFCSHeMiA== X-Received: by 2002:a63:2115:0:b0:373:7f7c:8699 with SMTP id h21-20020a632115000000b003737f7c8699mr11626276pgh.156.1645333817186; Sat, 19 Feb 2022 21:10:17 -0800 (PST) Received: from localhost.localdomain ([122.162.118.38]) by smtp.gmail.com with ESMTPSA id 84sm7602730pfx.181.2022.02.19.21.10.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Feb 2022 21:10:16 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v3 5/6] RISC-V: Use IPIs for remote TLB flush when possible Date: Sun, 20 Feb 2022 10:38:53 +0530 Message-Id: <20220220050854.743420-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220220050854.743420-1-apatel@ventanamicro.com> References: <20220220050854.743420-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220219_211017_994135_AE6F58C0 X-CRM114-Status: GOOD ( 14.86 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org If IPI calls are injected using SBI IPI calls then remote TLB flush using SBI RFENCE calls is much faster because using IPIs for remote TLB flush would still endup as SBI IPI calls with extra processing on kernel side. It is now possible to have specialized hardware (such as RISC-V AIA and RISC-V ACLINT) which allows S-mode software to directly inject IPIs without any assistance from M-mode runtime firmware. This patch extends remote TLB flush functions to use IPIs whenever underlying IPI operations are suitable for remote FENCEs. Signed-off-by: Anup Patel --- arch/riscv/mm/tlbflush.c | 93 +++++++++++++++++++++++++++++++++------- 1 file changed, 78 insertions(+), 15 deletions(-) diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 37ed760d007c..27a7db8eb2c4 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -23,14 +23,62 @@ static inline void local_flush_tlb_page_asid(unsigned long addr, : "memory"); } +static inline void local_flush_tlb_range(unsigned long start, + unsigned long size, unsigned long stride) +{ + if (size <= stride) + local_flush_tlb_page(start); + else + local_flush_tlb_all(); +} + +static inline void local_flush_tlb_range_asid(unsigned long start, + unsigned long size, unsigned long stride, unsigned long asid) +{ + if (size <= stride) + local_flush_tlb_page_asid(start, asid); + else + local_flush_tlb_all_asid(asid); +} + +static void __ipi_flush_tlb_all(void *info) +{ + local_flush_tlb_all(); +} + void flush_tlb_all(void) { - sbi_remote_sfence_vma(NULL, 0, -1); + if (riscv_use_ipi_for_rfence()) + on_each_cpu(__ipi_flush_tlb_all, NULL, 1); + else + sbi_remote_sfence_vma(NULL, 0, -1); +} + +struct flush_tlb_range_data { + unsigned long asid; + unsigned long start; + unsigned long size; + unsigned long stride; +}; + +static void __ipi_flush_tlb_range_asid(void *info) +{ + struct flush_tlb_range_data *d = info; + + local_flush_tlb_range_asid(d->start, d->size, d->stride, d->asid); +} + +static void __ipi_flush_tlb_range(void *info) +{ + struct flush_tlb_range_data *d = info; + + local_flush_tlb_range(d->start, d->size, d->stride); } -static void __sbi_tlb_flush_range(struct mm_struct *mm, unsigned long start, - unsigned long size, unsigned long stride) +static void __flush_tlb_range(struct mm_struct *mm, unsigned long start, + unsigned long size, unsigned long stride) { + struct flush_tlb_range_data ftd; struct cpumask *cmask = mm_cpumask(mm); unsigned int cpuid; bool broadcast; @@ -45,19 +93,34 @@ static void __sbi_tlb_flush_range(struct mm_struct *mm, unsigned long start, unsigned long asid = atomic_long_read(&mm->context.id); if (broadcast) { - sbi_remote_sfence_vma_asid(cmask, start, size, asid); - } else if (size <= stride) { - local_flush_tlb_page_asid(start, asid); + if (riscv_use_ipi_for_rfence()) { + ftd.asid = asid; + ftd.start = start; + ftd.size = size; + ftd.stride = stride; + on_each_cpu_mask(cmask, + __ipi_flush_tlb_range_asid, + &ftd, 1); + } else + sbi_remote_sfence_vma_asid(cmask, + start, size, asid); } else { - local_flush_tlb_all_asid(asid); + local_flush_tlb_range_asid(start, size, stride, asid); } } else { if (broadcast) { - sbi_remote_sfence_vma(cmask, start, size); - } else if (size <= stride) { - local_flush_tlb_page(start); + if (riscv_use_ipi_for_rfence()) { + ftd.asid = 0; + ftd.start = start; + ftd.size = size; + ftd.stride = stride; + on_each_cpu_mask(cmask, + __ipi_flush_tlb_range, + &ftd, 1); + } else + sbi_remote_sfence_vma(cmask, start, size); } else { - local_flush_tlb_all(); + local_flush_tlb_range(start, size, stride); } } @@ -66,23 +129,23 @@ static void __sbi_tlb_flush_range(struct mm_struct *mm, unsigned long start, void flush_tlb_mm(struct mm_struct *mm) { - __sbi_tlb_flush_range(mm, 0, -1, PAGE_SIZE); + __flush_tlb_range(mm, 0, -1, PAGE_SIZE); } void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) { - __sbi_tlb_flush_range(vma->vm_mm, addr, PAGE_SIZE, PAGE_SIZE); + __flush_tlb_range(vma->vm_mm, addr, PAGE_SIZE, PAGE_SIZE); } void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - __sbi_tlb_flush_range(vma->vm_mm, start, end - start, PAGE_SIZE); + __flush_tlb_range(vma->vm_mm, start, end - start, PAGE_SIZE); } #ifdef CONFIG_TRANSPARENT_HUGEPAGE void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - __sbi_tlb_flush_range(vma->vm_mm, start, end - start, PMD_SIZE); + __flush_tlb_range(vma->vm_mm, start, end - start, PMD_SIZE); } #endif