From patchwork Sat Mar 19 03:54:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 12786062 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 42C7CC4332F for ; Sat, 19 Mar 2022 03:55:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=updKBDp1kxoTzWml9c6EkKRUw0DHFQTLrXZJbMStjbQ=; b=SX/TGpQ1iUGJJy 71WxcGaYnjIbufGhyoQoZTATbSPftQxXWJStdKh0LJNGw9KVCUQ9t1WZLQe89NFuECh9UkJtxJucB myLZ3RKbHXFODZLmVlnMjo6GmDFTlJO6gBNKfMaM2+ebEUpL1/tmfPb8POYASHOxoeLktEzJ1Iq1L WCnMi7iCt+VOH+AKoyzLEHXr2q6iZUqEz4WR2+IUYAQrSsI+m3fcm6S8nCiSZ9F9WByxdBueCq5Vo WoTgrrPc84V+9O00aiDx5HF+O0u8f7NdxZoGSF0H94A65PxWvE4wcPPtr4ls11hZVaIsLPBBiqaWA 7kGxuLdWPVIqGBKlBtdA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nVQBZ-003BLa-Lj; Sat, 19 Mar 2022 03:55:25 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nVQBW-003BJp-Km for linux-riscv@lists.infradead.org; Sat, 19 Mar 2022 03:55:24 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 37212B82153; Sat, 19 Mar 2022 03:55:21 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 240B6C340F2; Sat, 19 Mar 2022 03:55:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1647662119; bh=JDXWg1zwYrTJg3qBN3Fpv5jBQ9oDxemcN/lCbJ/1qRs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=S2bzTd/C+ZXf8yaJXh9wIel+GNoB5VzxQHQ+lsT0C/jpzUh44QempyUKV27fC6yXi VCjc5MTcBX33EGZ43vNLa9n5tfw/m7jfW46JLF66+Jt5raFxr5DmeXuUNFErSvGV0v Te47lwtw6Dt9AkvFZYWmn07CzWaLxlE1lc7/O3YSfe51yID6iig2+CO7S2wR7lLaUs 1a0SzAEwFd4Cl/sF9zczXXp3j3302vaJsUAwIA5X02E43rfEb5Bd4A93USQs5StFo4 +KxpxBiWG4NV+6UEbOg0dZrEomY4sZER7KkzZ4XN5Snkc/L4T+jguAQkE8l3qsARBb NNOBN9XBNA2Lw== From: guoren@kernel.org To: guoren@kernel.org, palmer@dabbelt.com, arnd@arndb.de, boqun.feng@gmail.com, longman@redhat.com, peterz@infradead.org Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-csky@vger.kernel.org, openrisc@lists.librecores.org, Palmer Dabbelt Subject: [PATCH V2 2/5] asm-generic: qspinlock: Indicate the use of mixed-size atomics Date: Sat, 19 Mar 2022 11:54:54 +0800 Message-Id: <20220319035457.2214979-3-guoren@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220319035457.2214979-1-guoren@kernel.org> References: <20220319035457.2214979-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220318_205523_027309_A356133F X-CRM114-Status: GOOD ( 12.31 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Peter Zijlstra The qspinlock implementation depends on having well behaved mixed-size atomics. This is true on the more widely-used platforms, but these requirements are somewhat subtle and may not be satisfied by all the platforms that qspinlock is used on. Document these requirements, so ports that use qspinlock can more easily determine if they meet these requirements. Signed-off-by: Palmer Dabbelt Signed-off-by: Peter Zijlstra (Intel) Acked-by: Waiman Long --- include/asm-generic/qspinlock.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/include/asm-generic/qspinlock.h b/include/asm-generic/qspinlock.h index d74b13825501..a7a1296b0b4d 100644 --- a/include/asm-generic/qspinlock.h +++ b/include/asm-generic/qspinlock.h @@ -2,6 +2,36 @@ /* * Queued spinlock * + * A 'generic' spinlock implementation that is based on MCS locks. An + * architecture that's looking for a 'generic' spinlock, please first consider + * ticket-lock.h and only come looking here when you've considered all the + * constraints below and can show your hardware does actually perform better + * with qspinlock. + * + * + * It relies on atomic_*_release()/atomic_*_acquire() to be RCsc (or no weaker + * than RCtso if you're power), where regular code only expects atomic_t to be + * RCpc. + * + * It relies on a far greater (compared to ticket-lock.h) set of atomic + * operations to behave well together, please audit them carefully to ensure + * they all have forward progress. Many atomic operations may default to + * cmpxchg() loops which will not have good forward progress properties on + * LL/SC architectures. + * + * One notable example is atomic_fetch_or_acquire(), which x86 cannot (cheaply) + * do. Carefully read the patches that introduced queued_fetch_set_pending_acquire(). + * + * It also heavily relies on mixed size atomic operations, in specific it + * requires architectures to have xchg16; something which many LL/SC + * architectures need to implement as a 32bit and+or in order to satisfy the + * forward progress guarantees mentioned above. + * + * Further reading on mixed size atomics that might be relevant: + * + * http://www.cl.cam.ac.uk/~pes20/popl17/mixed-size.pdf + * + * * (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P. * (C) Copyright 2015 Hewlett-Packard Enterprise Development LP *