| Message ID | 20220411085916.941433-10-conor.dooley@microchip.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | More PolarFire SoC Fixes for 5.18 | expand |
On 11/04/2022 08:59, Conor Dooley wrote: > The 600M clock in the fabric is not the real reference, replace it with > a 125M clock which is the correct value for the icicle kit. Rename the > msspllclk node to mssrefclk since this is now the input to, not the > output of, the msspll clock. Control of the msspll clock has been moved > into the clock configurator, so add the register range for it to the clk > configurator. Finally, add a new output of the clock config block which > will provide the 1M reference clock for the MTIMER and the rtc. > > Fixes: feeb38685523 ("Update the Icicle Kit device tree") This is not the correct fixes tag. The one I meant to put was: Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree") However, that's the commit the RTC was added in but not the refclk. Can I have two fixes tags? The other one would be: Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") Although that seems like a sign that this should really be two commits... > Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > .../boot/dts/microchip/microchip-mpfs-icicle-kit.dts | 2 +- > arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 8 ++++---- > 2 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > index cd2fe80fa81a..3392153dd0f1 100644 > --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > @@ -45,7 +45,7 @@ ddrc_cache_hi: memory@1000000000 { > }; > > &refclk { > - clock-frequency = <600000000>; > + clock-frequency = <125000000>; > }; > > &mmuart1 { > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > index 3b48b7f35410..746c4d4e7686 100644 > --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > @@ -141,7 +141,7 @@ cpu4_intc: interrupt-controller { > }; > }; > > - refclk: msspllclk { > + refclk: mssrefclk { > compatible = "fixed-clock"; > #clock-cells = <0>; > }; > @@ -190,7 +190,7 @@ plic: interrupt-controller@c000000 { > > clkcfg: clkcfg@20002000 { > compatible = "microchip,mpfs-clkcfg"; > - reg = <0x0 0x20002000 0x0 0x1000>; > + reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; > clocks = <&refclk>; > #clock-cells = <1>; > }; > @@ -393,8 +393,8 @@ rtc: rtc@20124000 { > reg = <0x0 0x20124000 0x0 0x1000>; > interrupt-parent = <&plic>; > interrupts = <80>, <81>; > - clocks = <&clkcfg CLK_RTC>; > - clock-names = "rtc"; > + clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>; > + clock-names = "rtc", "rtcref"; > status = "disabled"; > }; >
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts index cd2fe80fa81a..3392153dd0f1 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -45,7 +45,7 @@ ddrc_cache_hi: memory@1000000000 { }; &refclk { - clock-frequency = <600000000>; + clock-frequency = <125000000>; }; &mmuart1 { diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index 3b48b7f35410..746c4d4e7686 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -141,7 +141,7 @@ cpu4_intc: interrupt-controller { }; }; - refclk: msspllclk { + refclk: mssrefclk { compatible = "fixed-clock"; #clock-cells = <0>; }; @@ -190,7 +190,7 @@ plic: interrupt-controller@c000000 { clkcfg: clkcfg@20002000 { compatible = "microchip,mpfs-clkcfg"; - reg = <0x0 0x20002000 0x0 0x1000>; + reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; clocks = <&refclk>; #clock-cells = <1>; }; @@ -393,8 +393,8 @@ rtc: rtc@20124000 { reg = <0x0 0x20124000 0x0 0x1000>; interrupt-parent = <&plic>; interrupts = <80>, <81>; - clocks = <&clkcfg CLK_RTC>; - clock-names = "rtc"; + clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>; + clock-names = "rtc", "rtcref"; status = "disabled"; };
The 600M clock in the fabric is not the real reference, replace it with a 125M clock which is the correct value for the icicle kit. Rename the msspllclk node to mssrefclk since this is now the input to, not the output of, the msspll clock. Control of the msspll clock has been moved into the clock configurator, so add the register range for it to the clk configurator. Finally, add a new output of the clock config block which will provide the 1M reference clock for the MTIMER and the rtc. Fixes: feeb38685523 ("Update the Icicle Kit device tree") Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- .../boot/dts/microchip/microchip-mpfs-icicle-kit.dts | 2 +- arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-)