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[1/1] RISC-V: defconfigs: add VITESSE_PHY

Message ID 20220419135807.164266-1-heinrich.schuchardt@canonical.com (mailing list archive)
State New, archived
Headers show
Series [1/1] RISC-V: defconfigs: add VITESSE_PHY | expand

Commit Message

Heinrich Schuchardt April 19, 2022, 1:58 p.m. UTC
The PolarFire-SoC Icicle Kit uses a Vitesse VSC8662 dual port PHY.

Enable CONFIG_VITESSE_PHY by default to provide network.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)
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Patch

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 30e3017f22bc..12908aa7766e 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -63,6 +63,7 @@  CONFIG_MACB=y
 CONFIG_E1000E=y
 CONFIG_R8169=y
 CONFIG_MICROSEMI_PHY=y
+CONFIG_VITESSE_PHY=m
 CONFIG_INPUT_MOUSEDEV=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y