From patchwork Fri Apr 29 10:40:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12831798 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AC6ECC433F5 for ; Fri, 29 Apr 2022 10:42:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=tdFnmE9pcYBZ9juOF8QJ+DtcSAGyKelO2FhgH+MucmY=; b=aE0d/g4dQj/AJh GN+is0kMXG5QQfcpNMoH84ZGesrU76Zv0mPEf0xxpF0bs99/uDkQ5jCmW65gftNVIo4zpuEmpnAVZ zbEEt4tVK/PUp6JAAB8bmJFhBvcWH7M/zqwzOJ0cdLAeRSPincBoPPxGLmRC8IzLqAwOLCdO7I47D 5Unr9y4TIQVlnISUQsJrv78e6gXkRCn3Z27Z8jMSU1s52R1k+ZUrnSXTbmQB9g1L6uH+598OBr8hx kyX4oAFNSuS+fuz7OS0+1bND4bKYJjgpfermn6QX7/AU+SrzUL1umq3i0wTeR8thvnkp8250391yg 7yKglTWJyoBe/+Q6PMuQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nkO4W-00ArVa-H0; Fri, 29 Apr 2022 10:42:00 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nkO4M-00ArMu-RK for linux-riscv@lists.infradead.org; Fri, 29 Apr 2022 10:41:53 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1651228910; x=1682764910; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Cv32FDml94cqqpdihITDsM5k1vOOBbEYHDCibMtfobU=; b=MSZ3n1yxiYfkwFJwwHPll+G0yaiVZwonvNoLbSuD3uVwCz6MHTbq0NxH 9WZ+P3oKNBvIh+B1jC4m9f0OS+LToFTCBsiAovtR692ur20igShkIh3Eo 0GE3f7LQT63cky6250EsnEnoZ4gTqp8DY/ao5Iu41DIbGy3FBtqymqzSG aABILnq3SUdzuCtKkAmwrSPx3l1JDZtYnCYkb80JZ2Srts4VBJXY+wMfI wckTWjbv1bpHj7JNOQ4XSZ1+BNMVyMMyniOwAo/Vi0NDTZFUwm9ZIi+V2 3r5NTsBicIPwoDXtH+hvBFQXz243SoTbmpYJbKQ+BY98VfEZjlcAtqDKS A==; X-IronPort-AV: E=Sophos;i="5.91,298,1647327600"; d="scan'208";a="154297321" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Apr 2022 03:41:50 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 29 Apr 2022 03:41:49 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 29 Apr 2022 03:41:47 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Daire McNamara , Cyril Jean , , , , "Arnd Bergmann" Subject: [PATCH v1 8/8] riscv: dts: microchip: add the sundance polarberry Date: Fri, 29 Apr 2022 11:40:41 +0100 Message-ID: <20220429104040.197161-9-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.2 In-Reply-To: <20220429104040.197161-1-conor.dooley@microchip.com> References: <20220429104040.197161-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220429_034150_994401_314F902B X-CRM114-Status: GOOD ( 13.86 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add a minimal device tree for the PolarFire SoC based Sundance PolarBerry. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/Makefile | 1 + .../dts/microchip/mpfs-polarberry-fabric.dtsi | 16 ++++ .../boot/dts/microchip/mpfs-polarberry.dts | 95 +++++++++++++++++++ 3 files changed, 112 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile index af3a5059b350..39aae7b04f1c 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi new file mode 100644 index 000000000000..49380c428ec9 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2022 Microchip Technology Inc */ + +/ { + fabric_clk3: fabric-clk3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <62500000>; + }; + + fabric_clk1: fabric-clk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts new file mode 100644 index 000000000000..8c635f3358a5 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2022 Microchip Technology Inc */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-polarberry-fabric.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define MTIMER_FREQ 1000000 + +/ { + model = "Sundance PolarBerry"; + compatible = "sundance,polarberry", "microchip,mpfs"; + + aliases { + serial0 = &mmuart0; + ethernet0 = &mac0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + timebase-frequency = ; + }; + + ddrc_cache_lo: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x2e000000>; + status = "okay"; + }; + + ddrc_cache_hi: memory@1000000000 { + device_type = "memory"; + reg = <0x10 0x00000000 0x0 0xC0000000>; + status = "okay"; + }; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&mmuart0 { + status = "okay"; +}; + +&mmc { + status = "okay"; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + card-detect-delay = <200>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +}; + +&mac1 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&phy1>; + phy1: ethernet-phy@5 { + reg = <5>; + ti,fifo-depth = <0x01>; + }; + phy0: ethernet-phy@4 { + reg = <4>; + ti,fifo-depth = <0x01>; + }; +}; + +&mac0 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&phy0>; +}; + +&rtc { + status = "okay"; +}; + +&mbox { + status = "okay"; +}; + +&syscontroller { + status = "okay"; +};