| Message ID | 20220615211415.3111271-1-daolu@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v3] arch/riscv: add Zihintpause support | expand |
On 6/15/22 4:14 PM, Dao Lu wrote: > Implement support for the ZiHintPause extension. > > The PAUSE instruction is a HINT that indicates the current hart’s rate > of instruction retirement should be temporarily reduced or paused. > > Reviewed-by: Heiko Stuebner <heiko@sntech.de> > Tested-by: Heiko Stuebner <heiko@sntech.de> > Signed-off-by: Dao Lu <daolu@rivosinc.com> > --- > > v1 -> v2: > Remove the usage of static branch, use PAUSE if toolchain supports it > v2 -> v3: > Added the static branch back, cpu_relax() behavior is unchanged if either the > system or the toolchain does not support ZiHintPause > --- > arch/riscv/Makefile | 4 ++++ > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/include/asm/vdso/processor.h | 19 ++++++++++++++++--- > arch/riscv/kernel/cpu.c | 1 + > arch/riscv/kernel/cpufeature.c | 8 ++++++++ > 5 files changed, 30 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile > index 34cf8a598617..6ddacc6f44b9 100644 > --- a/arch/riscv/Makefile > +++ b/arch/riscv/Makefile > @@ -56,6 +56,10 @@ riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c > toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei) > riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei > > +# Check if the toolchain supports Zihintpause extension > +toolchain-supports-zihintpause := $(call cc-option-yn, -march=$(riscv-march-y)_zihintpause) > +riscv-march-$(toolchain-supports-zihintpause) := $(riscv-march-y)_zihintpause > + > KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y)) > KBUILD_AFLAGS += -march=$(riscv-march-y) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 4e2486881840..f24f4f8c9144 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -53,6 +53,7 @@ extern unsigned long elf_hwcap; > enum riscv_isa_ext_id { > RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, > RISCV_ISA_EXT_SVPBMT, > + RISCV_ISA_EXT_ZIHINTPAUSE, > RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, > }; > > diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/asm/vdso/processor.h > index 134388cbaaa1..314ec17c40d8 100644 > --- a/arch/riscv/include/asm/vdso/processor.h > +++ b/arch/riscv/include/asm/vdso/processor.h > @@ -4,15 +4,28 @@ > > #ifndef __ASSEMBLY__ > > +#include <linux/jump_label.h> > #include <asm/barrier.h> > +#include <asm/hwcap.h> > > +extern struct static_key_false riscv_pause_available; > static inline void cpu_relax(void) > { > + if (!static_branch_likely(&riscv_pause_available)) { > #ifdef __riscv_muldiv > - int dummy; > - /* In lieu of a halt instruction, induce a long-latency stall. */ > - __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy)); > + int dummy; > + /* In lieu of a halt instruction, induce a long-latency stall. */ > + __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy)); > #endif > +#ifdef __riscv_zihintpause > + } else { > + /* > + * Reduce instruction retirement. > + * This assumes the PC changes. > + */ > + __asm__ __volatile__ ("pause"); > +#endif > + } > barrier(); > } > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index fba9e9f46a8c..a123e92b14dd 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -89,6 +89,7 @@ int riscv_of_parent_hartid(struct device_node *node) > static struct riscv_isa_ext_data isa_ext_arr[] = { > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), > + __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), > __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), > }; > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index a6f62a6d1edd..78c284c487e8 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -30,6 +30,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; > #ifdef CONFIG_FPU > __ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu); > #endif > +DEFINE_STATIC_KEY_FALSE(riscv_pause_available); > +EXPORT_SYMBOL_GPL(riscv_pause_available); This patch should probably be rebased to use the unified static key mechanism[1], since that patch has now been merged. Regards, Samuel [1]: https://lore.kernel.org/linux-riscv/20220522153543.2656-2-jszhang@kernel.org/
Will look at rebasing to use the unified static key mechanism for the next version. Regards, Dao On Thu, Jun 16, 2022 at 8:49 PM Samuel Holland <samuel@sholland.org> wrote: > > On 6/15/22 4:14 PM, Dao Lu wrote: > > Implement support for the ZiHintPause extension. > > > > The PAUSE instruction is a HINT that indicates the current hart’s rate > > of instruction retirement should be temporarily reduced or paused. > > > > Reviewed-by: Heiko Stuebner <heiko@sntech.de> > > Tested-by: Heiko Stuebner <heiko@sntech.de> > > Signed-off-by: Dao Lu <daolu@rivosinc.com> > > --- > > > > v1 -> v2: > > Remove the usage of static branch, use PAUSE if toolchain supports it > > v2 -> v3: > > Added the static branch back, cpu_relax() behavior is unchanged if either the > > system or the toolchain does not support ZiHintPause > > --- > > arch/riscv/Makefile | 4 ++++ > > arch/riscv/include/asm/hwcap.h | 1 + > > arch/riscv/include/asm/vdso/processor.h | 19 ++++++++++++++++--- > > arch/riscv/kernel/cpu.c | 1 + > > arch/riscv/kernel/cpufeature.c | 8 ++++++++ > > 5 files changed, 30 insertions(+), 3 deletions(-) > > > > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile > > index 34cf8a598617..6ddacc6f44b9 100644 > > --- a/arch/riscv/Makefile > > +++ b/arch/riscv/Makefile > > @@ -56,6 +56,10 @@ riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c > > toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei) > > riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei > > > > +# Check if the toolchain supports Zihintpause extension > > +toolchain-supports-zihintpause := $(call cc-option-yn, -march=$(riscv-march-y)_zihintpause) > > +riscv-march-$(toolchain-supports-zihintpause) := $(riscv-march-y)_zihintpause > > + > > KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y)) > > KBUILD_AFLAGS += -march=$(riscv-march-y) > > > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > > index 4e2486881840..f24f4f8c9144 100644 > > --- a/arch/riscv/include/asm/hwcap.h > > +++ b/arch/riscv/include/asm/hwcap.h > > @@ -53,6 +53,7 @@ extern unsigned long elf_hwcap; > > enum riscv_isa_ext_id { > > RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, > > RISCV_ISA_EXT_SVPBMT, > > + RISCV_ISA_EXT_ZIHINTPAUSE, > > RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, > > }; > > > > diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/asm/vdso/processor.h > > index 134388cbaaa1..314ec17c40d8 100644 > > --- a/arch/riscv/include/asm/vdso/processor.h > > +++ b/arch/riscv/include/asm/vdso/processor.h > > @@ -4,15 +4,28 @@ > > > > #ifndef __ASSEMBLY__ > > > > +#include <linux/jump_label.h> > > #include <asm/barrier.h> > > +#include <asm/hwcap.h> > > > > +extern struct static_key_false riscv_pause_available; > > static inline void cpu_relax(void) > > { > > + if (!static_branch_likely(&riscv_pause_available)) { > > #ifdef __riscv_muldiv > > - int dummy; > > - /* In lieu of a halt instruction, induce a long-latency stall. */ > > - __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy)); > > + int dummy; > > + /* In lieu of a halt instruction, induce a long-latency stall. */ > > + __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy)); > > #endif > > +#ifdef __riscv_zihintpause > > + } else { > > + /* > > + * Reduce instruction retirement. > > + * This assumes the PC changes. > > + */ > > + __asm__ __volatile__ ("pause"); > > +#endif > > + } > > barrier(); > > } > > > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > > index fba9e9f46a8c..a123e92b14dd 100644 > > --- a/arch/riscv/kernel/cpu.c > > +++ b/arch/riscv/kernel/cpu.c > > @@ -89,6 +89,7 @@ int riscv_of_parent_hartid(struct device_node *node) > > static struct riscv_isa_ext_data isa_ext_arr[] = { > > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > > __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), > > + __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), > > __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), > > }; > > > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > > index a6f62a6d1edd..78c284c487e8 100644 > > --- a/arch/riscv/kernel/cpufeature.c > > +++ b/arch/riscv/kernel/cpufeature.c > > @@ -30,6 +30,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; > > #ifdef CONFIG_FPU > > __ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu); > > #endif > > +DEFINE_STATIC_KEY_FALSE(riscv_pause_available); > > +EXPORT_SYMBOL_GPL(riscv_pause_available); > > This patch should probably be rebased to use the unified static key > mechanism[1], since that patch has now been merged. > > Regards, > Samuel > > [1]: https://lore.kernel.org/linux-riscv/20220522153543.2656-2-jszhang@kernel.org/
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 34cf8a598617..6ddacc6f44b9 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -56,6 +56,10 @@ riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei) riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei +# Check if the toolchain supports Zihintpause extension +toolchain-supports-zihintpause := $(call cc-option-yn, -march=$(riscv-march-y)_zihintpause) +riscv-march-$(toolchain-supports-zihintpause) := $(riscv-march-y)_zihintpause + KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y)) KBUILD_AFLAGS += -march=$(riscv-march-y) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 4e2486881840..f24f4f8c9144 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -53,6 +53,7 @@ extern unsigned long elf_hwcap; enum riscv_isa_ext_id { RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, RISCV_ISA_EXT_SVPBMT, + RISCV_ISA_EXT_ZIHINTPAUSE, RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/asm/vdso/processor.h index 134388cbaaa1..314ec17c40d8 100644 --- a/arch/riscv/include/asm/vdso/processor.h +++ b/arch/riscv/include/asm/vdso/processor.h @@ -4,15 +4,28 @@ #ifndef __ASSEMBLY__ +#include <linux/jump_label.h> #include <asm/barrier.h> +#include <asm/hwcap.h> +extern struct static_key_false riscv_pause_available; static inline void cpu_relax(void) { + if (!static_branch_likely(&riscv_pause_available)) { #ifdef __riscv_muldiv - int dummy; - /* In lieu of a halt instruction, induce a long-latency stall. */ - __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy)); + int dummy; + /* In lieu of a halt instruction, induce a long-latency stall. */ + __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy)); #endif +#ifdef __riscv_zihintpause + } else { + /* + * Reduce instruction retirement. + * This assumes the PC changes. + */ + __asm__ __volatile__ ("pause"); +#endif + } barrier(); } diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index fba9e9f46a8c..a123e92b14dd 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -89,6 +89,7 @@ int riscv_of_parent_hartid(struct device_node *node) static struct riscv_isa_ext_data isa_ext_arr[] = { __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), + __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), }; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index a6f62a6d1edd..78c284c487e8 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -30,6 +30,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; #ifdef CONFIG_FPU __ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu); #endif +DEFINE_STATIC_KEY_FALSE(riscv_pause_available); +EXPORT_SYMBOL_GPL(riscv_pause_available); /** * riscv_isa_extension_base() - Get base extension word @@ -199,6 +201,7 @@ void __init riscv_fill_hwcap(void) } else { SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); + SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); } #undef SET_ISA_EXT_MAP } @@ -219,6 +222,11 @@ void __init riscv_fill_hwcap(void) bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX); } +#ifdef __riscv_zihintpause + if (__riscv_isa_extension_available(riscv_isa, RISCV_ISA_EXT_ZIHINTPAUSE)) + static_branch_enable(&riscv_pause_available); +#endif + /* We don't support systems with F but without D, so mask those out * here. */ if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) {