[RESEND,v4] MAINTAINERS: add polarfire rng, pci and clock drivers

Commit Message

Conor Dooley June 22, 2022, 10:58 p.m. UTC

From: Conor Dooley <[e-mail]>

Hardware random, PCI and clock drivers for the PolarFire SoC have been
upstreamed but are not covered by the MAINTAINERS entry, so add them.
Daire is the author of the clock & PCI drivers, so add him as a
maintainer in place of Lewis.

Acked-by: Bjorn Helgaas <[e-mail]>
Acked-by: Stephen Boyd <[e-mail]>
Signed-off-by: Conor Dooley <[e-mail]>
---
 MAINTAINERS | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

Comments

Conor Dooley July 7, 2022, 1:30 p.m. UTC | #1

On 22/06/2022 23:58, Conor Dooley wrote:
> From: Conor Dooley <[e-mail]>
> 
> Hardware random, PCI and clock drivers for the PolarFire SoC have been
> upstreamed but are not covered by the MAINTAINERS entry, so add them.
> Daire is the author of the clock & PCI drivers, so add him as a
> maintainer in place of Lewis.
> 
> Acked-by: Bjorn Helgaas <[e-mail]>
> Acked-by: Stephen Boyd <[e-mail]>
> Signed-off-by: Conor Dooley <[e-mail]>

Arnd, Palmer:
Does the SoC tree make more sense for this patch?
I am missing an ack from Herbert (but I don't think that's blocking
for a MAINTAINERS update to my own entry?).

If SoC is the better option, should I resend this to [e-mail]?
Unfortunately, since I originally sent this patch there have been
other changes to this entry that will conflict in -next (all are
additions so easily resolved...).

I was hoping to get this patch applied to v5.19-rc(foo) since we
never added maintainers entries for these drivers rather than wait
for v5.20.

If you (plural) would rather wait for v5.20, I can resubmit this patch
after v5.20-mw1 with an additional i2c entry (if the driver is applied)
that already has an ack from Wolfram.

Thanks,
Conor.

> ---
>   MAINTAINERS | 5 ++++-
>   1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index a6d3bd9d2a8d..01a7bfa49bdc 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -17136,12 +17136,15 @@ N:	riscv
>   K:	riscv
>   
>   RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
> -M:	Lewis Hanly <[e-mail]>
>   M:	Conor Dooley <[e-mail]>
> +M:	Daire McNamara <[e-mail]>
>   L:	[e-mail]
>   S:	Supported
>   F:	arch/riscv/boot/dts/microchip/
> +F:	drivers/char/hw_random/mpfs-rng.c
> +F:	drivers/clk/microchip/clk-mpfs.c
>   F:	drivers/mailbox/mailbox-mpfs.c
> +F:	drivers/pci/controller/pcie-microchip-host.c
>   F:	drivers/soc/microchip/
>   F:	include/soc/microchip/mpfs.h
>

Arnd Bergmann July 7, 2022, 1:37 p.m. UTC | #2

On Thu, Jul 7, 2022 at 3:30 PM <[e-mail]> wrote:
>
> On 22/06/2022 23:58, Conor Dooley wrote:
> > From: Conor Dooley <[e-mail]>
> >
> > Hardware random, PCI and clock drivers for the PolarFire SoC have been
> > upstreamed but are not covered by the MAINTAINERS entry, so add them.
> > Daire is the author of the clock & PCI drivers, so add him as a
> > maintainer in place of Lewis.
> >
> > Acked-by: Bjorn Helgaas <[e-mail]>
> > Acked-by: Stephen Boyd <[e-mail]>
> > Signed-off-by: Conor Dooley <[e-mail]>
>
> Arnd, Palmer:
> Does the SoC tree make more sense for this patch?
> I am missing an ack from Herbert (but I don't think that's blocking
> for a MAINTAINERS update to my own entry?).
>
> If SoC is the better option, should I resend this to [e-mail]?
> Unfortunately, since I originally sent this patch there have been
> other changes to this entry that will conflict in -next (all are
> additions so easily resolved...).
>
> I was hoping to get this patch applied to v5.19-rc(foo) since we
> never added maintainers entries for these drivers rather than wait
> for v5.20.
>
> If you (plural) would rather wait for v5.20, I can resubmit this patch
> after v5.20-mw1 with an additional i2c entry (if the driver is applied)
> that already has an ack from Wolfram.

I tend to take MAINTAINERS updates as bugfixes in the soc tre
(for 5.19), and I can pick it up if you send it to [e-mail].

There should never be a need to wait for the merge window
with these updates, it's either a bugfix (for 5.19) or for the current
-next cycle (5.20).

       Arnd

Conor Dooley July 7, 2022, 2:07 p.m. UTC | #3

On 07/07/2022 14:37, Arnd Bergmann wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On Thu, Jul 7, 2022 at 3:30 PM <[e-mail]> wrote:
>>
>> On 22/06/2022 23:58, Conor Dooley wrote:
>>> From: Conor Dooley <[e-mail]>
>>>
>>> Hardware random, PCI and clock drivers for the PolarFire SoC have been
>>> upstreamed but are not covered by the MAINTAINERS entry, so add them.
>>> Daire is the author of the clock & PCI drivers, so add him as a
>>> maintainer in place of Lewis.
>>>
>>> Acked-by: Bjorn Helgaas <[e-mail]>
>>> Acked-by: Stephen Boyd <[e-mail]>
>>> Signed-off-by: Conor Dooley <[e-mail]>
>>
>> Arnd, Palmer:
>> Does the SoC tree make more sense for this patch?
>> I am missing an ack from Herbert (but I don't think that's blocking
>> for a MAINTAINERS update to my own entry?).
>>
>> If SoC is the better option, should I resend this to [e-mail]?
>> Unfortunately, since I originally sent this patch there have been
>> other changes to this entry that will conflict in -next (all are
>> additions so easily resolved...).
>>
>> I was hoping to get this patch applied to v5.19-rc(foo) since we
>> never added maintainers entries for these drivers rather than wait
>> for v5.20.
>>
>> If you (plural) would rather wait for v5.20, I can resubmit this patch
>> after v5.20-mw1 with an additional i2c entry (if the driver is applied)
>> that already has an ack from Wolfram.
> 
> I tend to take MAINTAINERS updates as bugfixes in the soc tre
> (for 5.19), and I can pick it up if you send it to [e-mail].

Cool, I will resend to [e-mail].

> 
> There should never be a need to wait for the merge window
> with these updates, it's either a bugfix (for 5.19) or for the current
> -next cycle (5.20).

I was just suggesting that to avoid conflicts in linux-next
but they will/can be trivially resolved.

Thanks Arnd.
Conor.

Herbert Xu July 8, 2022, 5:14 a.m. UTC | #4

On Thu, Jul 07, 2022 at 01:30:27PM +0000, [e-mail] wrote:
> On 22/06/2022 23:58, Conor Dooley wrote:
> > From: Conor Dooley <[e-mail]>
> > 
> > Hardware random, PCI and clock drivers for the PolarFire SoC have been
> > upstreamed but are not covered by the MAINTAINERS entry, so add them.
> > Daire is the author of the clock & PCI drivers, so add him as a
> > maintainer in place of Lewis.
> > 
> > Acked-by: Bjorn Helgaas <[e-mail]>
> > Acked-by: Stephen Boyd <[e-mail]>
> > Signed-off-by: Conor Dooley <[e-mail]>
> 
> Arnd, Palmer:
> Does the SoC tree make more sense for this patch?
> I am missing an ack from Herbert (but I don't think that's blocking
> for a MAINTAINERS update to my own entry?).

I'm not sure why an ack is needed from me since the entry doesn't
intersect with crypto at all.  But FWIW

Acked-by: Herbert Xu <[e-mail]>

Cheers,

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index a6d3bd9d2a8d..01a7bfa49bdc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17136,12 +17136,15 @@  N:	riscv
 K:	riscv
 
 RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
-M:	Lewis Hanly <[e-mail]>
 M:	Conor Dooley <[e-mail]>
+M:	Daire McNamara <[e-mail]>
 L:	[e-mail]
 S:	Supported
 F:	arch/riscv/boot/dts/microchip/
+F:	drivers/char/hw_random/mpfs-rng.c
+F:	drivers/clk/microchip/clk-mpfs.c
 F:	drivers/mailbox/mailbox-mpfs.c
+F:	drivers/pci/controller/pcie-microchip-host.c
 F:	drivers/soc/microchip/
 F:	include/soc/microchip/mpfs.h