| Message ID | 20220630080532.323731-14-conor.dooley@microchip.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | PolarFire SoC reset controller & clock cleanups | expand |
On 30/06/2022 09:05, Conor Dooley wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > The cfg_clk struct is now just a redefinition of the clk_divider struct > with custom implentations of the ops, that implement an extra level of > redirection. Remove the custom struct and replace it with clk_divider. Looks like I forgot to assign the spinlock in this and the periph_clk patches. I'm respinning anyway to fix Philipp's comments on the reset controller & to drop the two net-next patches so I'll fix this too. Thanks, Conor. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > drivers/clk/microchip/clk-mpfs.c | 75 +++----------------------------- > 1 file changed, 7 insertions(+), 68 deletions(-) > > diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c > index e58d0bc4669a..c4d1c48d6d3d 100644 > --- a/drivers/clk/microchip/clk-mpfs.c > +++ b/drivers/clk/microchip/clk-mpfs.c > @@ -51,24 +51,13 @@ struct mpfs_msspll_hw_clock { > > #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw) > > -struct mpfs_cfg_clock { > - void __iomem *reg; > - const struct clk_div_table *table; > - u8 shift; > - u8 width; > - u8 flags; > -}; > - > struct mpfs_cfg_hw_clock { > - struct mpfs_cfg_clock cfg; > - struct clk_hw hw; > + struct clk_divider cfg; > struct clk_init_data init; > unsigned int id; > u32 reg_offset; > }; > > -#define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw) > - > struct mpfs_periph_clock { > void __iomem *reg; > u8 shift; > @@ -228,56 +217,6 @@ static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_c > * "CFG" clocks > */ > > -static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long prate) > -{ > - struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); > - struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; > - u32 val; > - > - val = readl_relaxed(cfg->reg) >> cfg->shift; > - val &= clk_div_mask(cfg->width); > - > - return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width); > -} > - > -static long mpfs_cfg_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) > -{ > - struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); > - struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; > - > - return divider_round_rate(hw, rate, prate, cfg->table, cfg->width, 0); > -} > - > -static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) > -{ > - struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); > - struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; > - unsigned long flags; > - u32 val; > - int divider_setting; > - > - divider_setting = divider_get_val(rate, prate, cfg->table, cfg->width, 0); > - > - if (divider_setting < 0) > - return divider_setting; > - > - spin_lock_irqsave(&mpfs_clk_lock, flags); > - val = readl_relaxed(cfg->reg); > - val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); > - val |= divider_setting << cfg->shift; > - writel_relaxed(val, cfg->reg); > - > - spin_unlock_irqrestore(&mpfs_clk_lock, flags); > - > - return 0; > -} > - > -static const struct clk_ops mpfs_clk_cfg_ops = { > - .recalc_rate = mpfs_cfg_clk_recalc_rate, > - .round_rate = mpfs_cfg_clk_round_rate, > - .set_rate = mpfs_cfg_clk_set_rate, > -}; > - > #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ > .id = _id, \ > .cfg.shift = _shift, \ > @@ -285,7 +224,7 @@ static const struct clk_ops mpfs_clk_cfg_ops = { > .cfg.table = _table, \ > .reg_offset = _offset, \ > .cfg.flags = _flags, \ > - .hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \ > + .cfg.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \ > } > > static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { > @@ -302,8 +241,8 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { > .cfg.table = mpfs_div_rtcref_table, > .reg_offset = REG_RTC_CLOCK_CR, > .cfg.flags = CLK_DIVIDER_ONE_BASED, > - .hw.init = > - CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops, 0), > + .cfg.hw.init = > + CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, 0), > } > }; > > @@ -317,13 +256,13 @@ static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock * > struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i]; > > cfg_hw->cfg.reg = data->base + cfg_hw->reg_offset; > - ret = devm_clk_hw_register(dev, &cfg_hw->hw); > + ret = devm_clk_hw_register(dev, &cfg_hw->cfg.hw); > if (ret) > return dev_err_probe(dev, ret, "failed to register clock id: %d\n", > cfg_hw->id); > > id = cfg_hw->id; > - data->hw_data.hws[id] = &cfg_hw->hw; > + data->hw_data.hws[id] = &cfg_hw->cfg.hw; > } > > return 0; > @@ -393,7 +332,7 @@ static const struct clk_ops mpfs_periph_clk_ops = { > _flags), \ > } > > -#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT].hw) > +#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT].cfg.hw) > > /* > * Critical clocks: > -- > 2.36.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index e58d0bc4669a..c4d1c48d6d3d 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -51,24 +51,13 @@ struct mpfs_msspll_hw_clock { #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw) -struct mpfs_cfg_clock { - void __iomem *reg; - const struct clk_div_table *table; - u8 shift; - u8 width; - u8 flags; -}; - struct mpfs_cfg_hw_clock { - struct mpfs_cfg_clock cfg; - struct clk_hw hw; + struct clk_divider cfg; struct clk_init_data init; unsigned int id; u32 reg_offset; }; -#define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw) - struct mpfs_periph_clock { void __iomem *reg; u8 shift; @@ -228,56 +217,6 @@ static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_c * "CFG" clocks */ -static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long prate) -{ - struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); - struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; - u32 val; - - val = readl_relaxed(cfg->reg) >> cfg->shift; - val &= clk_div_mask(cfg->width); - - return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width); -} - -static long mpfs_cfg_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) -{ - struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); - struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; - - return divider_round_rate(hw, rate, prate, cfg->table, cfg->width, 0); -} - -static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) -{ - struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); - struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; - unsigned long flags; - u32 val; - int divider_setting; - - divider_setting = divider_get_val(rate, prate, cfg->table, cfg->width, 0); - - if (divider_setting < 0) - return divider_setting; - - spin_lock_irqsave(&mpfs_clk_lock, flags); - val = readl_relaxed(cfg->reg); - val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); - val |= divider_setting << cfg->shift; - writel_relaxed(val, cfg->reg); - - spin_unlock_irqrestore(&mpfs_clk_lock, flags); - - return 0; -} - -static const struct clk_ops mpfs_clk_cfg_ops = { - .recalc_rate = mpfs_cfg_clk_recalc_rate, - .round_rate = mpfs_cfg_clk_round_rate, - .set_rate = mpfs_cfg_clk_set_rate, -}; - #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ .id = _id, \ .cfg.shift = _shift, \ @@ -285,7 +224,7 @@ static const struct clk_ops mpfs_clk_cfg_ops = { .cfg.table = _table, \ .reg_offset = _offset, \ .cfg.flags = _flags, \ - .hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \ + .cfg.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \ } static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { @@ -302,8 +241,8 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { .cfg.table = mpfs_div_rtcref_table, .reg_offset = REG_RTC_CLOCK_CR, .cfg.flags = CLK_DIVIDER_ONE_BASED, - .hw.init = - CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops, 0), + .cfg.hw.init = + CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, 0), } }; @@ -317,13 +256,13 @@ static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock * struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i]; cfg_hw->cfg.reg = data->base + cfg_hw->reg_offset; - ret = devm_clk_hw_register(dev, &cfg_hw->hw); + ret = devm_clk_hw_register(dev, &cfg_hw->cfg.hw); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", cfg_hw->id); id = cfg_hw->id; - data->hw_data.hws[id] = &cfg_hw->hw; + data->hw_data.hws[id] = &cfg_hw->cfg.hw; } return 0; @@ -393,7 +332,7 @@ static const struct clk_ops mpfs_periph_clk_ops = { _flags), \ } -#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT].hw) +#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT].cfg.hw) /* * Critical clocks:
The cfg_clk struct is now just a redefinition of the clk_divider struct with custom implentations of the ops, that implement an extra level of redirection. Remove the custom struct and replace it with clk_divider. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- drivers/clk/microchip/clk-mpfs.c | 75 +++----------------------------- 1 file changed, 7 insertions(+), 68 deletions(-)