From patchwork Mon Jul 4 12:15:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12905240 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E6442C433EF for ; Mon, 4 Jul 2022 12:17:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=YF04rJ2iTU/K4ADbSaratf/AH5TFsa0Us9z0LBXaVW4=; b=hsUWCYK2K3iA50 bzEIdnKzAMaTnr99f1UwIAL4N41r4VVnL2QvJQgdjTRqVu889FyS1dg/1zdqwjso1sHNzcqd/ED0+ wdLm51uk/6y//SsuaioH9Yyv9duRJvhyurFUkLxgQuMMXBve9Ik8zxYTcY4vejHAtfXWBMkQLujWn sT31gQqXG3X13S7g3xnMttTxw1WvkwjekfzTqiXbYPSi3HsLGW+WR4dSmzNN6LS0+umB/cEWU+edx G/wGVqeVxx51mj9fpOjgRUq/sjLNnu63UUQDou8TRWxgdAczk0wsgaOzYwzzhizxuM1jTqjJoJ2d1 vmQM9bWbcV4ZlJCAYsyw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o8L0j-008ffD-9q; Mon, 04 Jul 2022 12:17:05 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o8L0c-008fXZ-4S for linux-riscv@lists.infradead.org; Mon, 04 Jul 2022 12:16:59 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656937018; x=1688473018; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jypCj0+NdAqT0FeiSwpVevo69MKmHu5r7GP6Jh6Aj/U=; b=c97OCO3MGte6sYMyqYOQrM6x6GXcuNDfaGJDhijbUTd51CWcb6xfdql2 hViK6MZKtEnlAtes42+yBzlLdzIRMGUF7JadXjlI7Nd+mLh8RSPzeT+3k W3yVzcTnkqg/tRPG/PEE1xPlA453IDEyi0zCHm3UILKeQiiRPMGflbb1l zZ82OveATiLYK+6nD5M+1vmJsqDs1ABc23ng2/gjzLi9MzOZfemnVS0hy Eot7ljmdsDNi08mJ9Q+OTXO61TM9cOXWsgISecw7W3C2KMeRoYPhoEQA7 0N6plkZCl/LSsBF5YVZ8tHk0ArLzSsC6mhRl9s9Clo0ujweU7PmxVeZc+ g==; X-IronPort-AV: E=Sophos;i="5.92,243,1650956400"; d="scan'208";a="170686875" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 04 Jul 2022 05:16:58 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 4 Jul 2022 05:16:56 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 4 Jul 2022 05:16:54 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v2 12/12] clk: microchip: mpfs: convert periph_clk to clk_gate Date: Mon, 4 Jul 2022 13:15:59 +0100 Message-ID: <20220704121558.2088698-13-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220704121558.2088698-1-conor.dooley@microchip.com> References: <20220704121558.2088698-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220704_051658_266518_5EE8A8E1 X-CRM114-Status: GOOD ( 12.97 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org With the reset code moved to the recently added reset controller, there is no need for custom ops any longer. Remove the custom ops and the custom struct by converting to a clk_gate. Signed-off-by: Conor Dooley --- drivers/clk/microchip/clk-mpfs.c | 74 +++----------------------------- 1 file changed, 7 insertions(+), 67 deletions(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index 1d9e8c1e56b6..2d5585c6ef21 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -58,19 +58,11 @@ struct mpfs_cfg_hw_clock { u32 reg_offset; }; -struct mpfs_periph_clock { - void __iomem *reg; - u8 shift; -}; - struct mpfs_periph_hw_clock { - struct mpfs_periph_clock periph; - struct clk_hw hw; + struct clk_gate periph; unsigned int id; }; -#define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw) - /* * mpfs_clk_lock prevents anything else from writing to the * mpfs clk block while a software locked register is being written. @@ -273,64 +265,12 @@ static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock * * peripheral clocks - devices connected to axi or ahb buses. */ -static int mpfs_periph_clk_enable(struct clk_hw *hw) -{ - struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); - struct mpfs_periph_clock *periph = &periph_hw->periph; - u32 reg, val; - unsigned long flags; - - spin_lock_irqsave(&mpfs_clk_lock, flags); - - reg = readl_relaxed(periph->reg); - val = reg | (1u << periph->shift); - writel_relaxed(val, periph->reg); - - spin_unlock_irqrestore(&mpfs_clk_lock, flags); - - return 0; -} - -static void mpfs_periph_clk_disable(struct clk_hw *hw) -{ - struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); - struct mpfs_periph_clock *periph = &periph_hw->periph; - u32 reg, val; - unsigned long flags; - - spin_lock_irqsave(&mpfs_clk_lock, flags); - - reg = readl_relaxed(periph->reg); - val = reg & ~(1u << periph->shift); - writel_relaxed(val, periph->reg); - - spin_unlock_irqrestore(&mpfs_clk_lock, flags); -} - -static int mpfs_periph_clk_is_enabled(struct clk_hw *hw) -{ - struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); - struct mpfs_periph_clock *periph = &periph_hw->periph; - u32 reg; - - reg = readl_relaxed(periph->reg); - if (reg & (1u << periph->shift)) - return 1; - - return 0; -} - -static const struct clk_ops mpfs_periph_clk_ops = { - .enable = mpfs_periph_clk_enable, - .disable = mpfs_periph_clk_disable, - .is_enabled = mpfs_periph_clk_is_enabled, -}; - #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ - .id = _id, \ - .periph.shift = _shift, \ - .hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, \ + .id = _id, \ + .periph.bit_idx = _shift, \ + .periph.hw.init = CLK_HW_INIT_HW(_name, _parent, &clk_gate_ops, \ _flags), \ + .periph.lock = &mpfs_clk_lock, \ } #define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT].cfg.hw) @@ -389,13 +329,13 @@ static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_c struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i]; periph_hw->periph.reg = data->base + REG_SUBBLK_CLOCK_CR; - ret = devm_clk_hw_register(dev, &periph_hw->hw); + ret = devm_clk_hw_register(dev, &periph_hw->periph.hw); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", periph_hw->id); id = periph_hws[i].id; - data->hw_data.hws[id] = &periph_hw->hw; + data->hw_data.hws[id] = &periph_hw->periph.hw; } return 0;