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([51.37.234.167]) by smtp.gmail.com with ESMTPSA id bn24-20020a056000061800b0020fe35aec4bsm38625743wrb.70.2022.07.07.15.05.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 15:05:02 -0700 (PDT) From: Conor Dooley To: Paul Walmsley , Palmer Dabbelt , Palmer Dabbelt , Albert Ou , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , "Rafael J . Wysocki" Cc: Daire McNamara , Conor Dooley , Niklas Cassel , Damien Le Moal , Geert Uytterhoeven , Zong Li , Emil Renner Berthing , Jonas Hahnfeld , Guo Ren , Anup Patel , Atish Patra , Changbin Du , Heiko Stuebner , Philipp Tomsich , Rob Herring , Marc Zyngier , Viresh Kumar , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Brice Goglin Subject: [RFC 4/4] arm64: arch-topology move arm64 to the generic store_cpu_topology() Date: Thu, 7 Jul 2022 23:04:37 +0100 Message-Id: <20220707220436.4105443-5-mail@conchuod.ie> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220707220436.4105443-1-mail@conchuod.ie> References: <20220707220436.4105443-1-mail@conchuod.ie> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220707_150507_523403_C8C2EEDE X-CRM114-Status: GOOD ( 18.27 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley The default implementation of store_cpu_topology() was derived from the arm64 implementation, but with the mpidr bits removed. Extract the mpidr bits from the arch implementation to the callsites & use the generic version. Signed-off-by: Conor Dooley --- arch/arm64/kernel/smp.c | 16 +++++++++++++-- arch/arm64/kernel/topology.c | 40 ------------------------------------ 2 files changed, 14 insertions(+), 42 deletions(-) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 62ed361a4376..9e8acaa4c2f7 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -234,7 +234,12 @@ asmlinkage notrace void secondary_start_kernel(void) * Log the CPU info before it is marked online and might get read. */ cpuinfo_store_cpu(); - store_cpu_topology(cpu); + + /* + * Uniprocessor systems can rely on default topology values + */ + if (!(mpidr & MPIDR_UP_BITMASK)) + store_cpu_topology(cpu); /* * Enable GIC and timers. @@ -719,6 +724,7 @@ void __init smp_init_cpus(void) void __init smp_prepare_cpus(unsigned int max_cpus) { const struct cpu_operations *ops; + u64 mpidr; int err; unsigned int cpu; unsigned int this_cpu; @@ -726,7 +732,13 @@ void __init smp_prepare_cpus(unsigned int max_cpus) init_cpu_topology(); this_cpu = smp_processor_id(); - store_cpu_topology(this_cpu); + mpidr = read_cpuid_mpidr(); + + /* + * Uniprocessor systems can rely on default topology values + */ + if (!(mpidr & MPIDR_UP_BITMASK)) + store_cpu_topology(this_cpu); numa_store_cpu_info(this_cpu); numa_add_cpu(this_cpu); diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 869ffc4d4484..7889a00f5487 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -22,46 +22,6 @@ #include #include -void store_cpu_topology(unsigned int cpuid) -{ - struct cpu_topology *cpuid_topo = &cpu_topology[cpuid]; - u64 mpidr; - - if (cpuid_topo->package_id != -1) - goto topology_populated; - - mpidr = read_cpuid_mpidr(); - - /* Uniprocessor systems can rely on default topology values */ - if (mpidr & MPIDR_UP_BITMASK) - return; - - /* - * This would be the place to create cpu topology based on MPIDR. - * - * However, it cannot be trusted to depict the actual topology; some - * pieces of the architecture enforce an artificial cap on Aff0 values - * (e.g. GICv3's ICC_SGI1R_EL1 limits it to 15), leading to an - * artificial cycling of Aff1, Aff2 and Aff3 values. IOW, these end up - * having absolutely no relationship to the actual underlying system - * topology, and cannot be reasonably used as core / package ID. - * - * If the MT bit is set, Aff0 *could* be used to define a thread ID, but - * we still wouldn't be able to obtain a sane core ID. This means we - * need to entirely ignore MPIDR for any topology deduction. - */ - cpuid_topo->thread_id = -1; - cpuid_topo->core_id = cpuid; - cpuid_topo->package_id = cpu_to_node(cpuid); - - pr_debug("CPU%u: cluster %d core %d thread %d mpidr %#016llx\n", - cpuid, cpuid_topo->package_id, cpuid_topo->core_id, - cpuid_topo->thread_id, mpidr); - -topology_populated: - update_siblings_masks(cpuid); -} - #ifdef CONFIG_ACPI static bool __init acpi_cpu_is_threaded(int cpu) {