Message ID | 20220805162844.1554247-4-mail@conchuod.ie (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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([93.107.66.220]) by smtp.gmail.com with ESMTPSA id b10-20020a056000054a00b00220633d96f2sm5210086wrf.72.2022.08.05.09.29.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Aug 2022 09:29:06 -0700 (PDT) From: Conor Dooley <mail@conchuod.ie> To: Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>, Anup Patel <anup@brainfault.org>, Conor Dooley <conor.dooley@microchip.com>, Guo Ren <guoren@kernel.org>, Sagar Kadam <sagar.kadam@sifive.com>, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, qemu-riscv@nongnu.org, Rob Herring <robh@kernel.org> Subject: [PATCH 3/3] dt-bindings: riscv: add new riscv,isa strings for emulators Date: Fri, 5 Aug 2022 17:28:45 +0100 Message-Id: <20220805162844.1554247-4-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220805162844.1554247-1-mail@conchuod.ie> References: <20220805162844.1554247-1-mail@conchuod.ie> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220805_092910_951096_5720DF4B X-CRM114-Status: GOOD ( 12.60 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: <linux-riscv.lists.infradead.org> List-Unsubscribe: <http://lists.infradead.org/mailman/options/linux-riscv>, <mailto:linux-riscv-request@lists.infradead.org?subject=unsubscribe> List-Archive: <http://lists.infradead.org/pipermail/linux-riscv/> List-Post: <mailto:linux-riscv@lists.infradead.org> List-Help: <mailto:linux-riscv-request@lists.infradead.org?subject=help> List-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-riscv>, <mailto:linux-riscv-request@lists.infradead.org?subject=subscribe> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org |
Series |
Fix dt-validate issues on qemu dtbdumps due to dt-bindings
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expand
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diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d632ac76532e..59b942c5b9aa 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -77,6 +77,8 @@ properties: enum: - rv64imac - rv64imafdc + - rv64imafdch + - rv64imafdch_zicsr_zifencei_zba_zbb_zbc_zbs # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false