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Thu, 11 Aug 2022 21:29:38 -0700 (PDT) Received: from ThinkPad-T490.dc1.ventanamicro.com ([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id h29-20020aa79f5d000000b0052d981e7842sm524904pfr.208.2022.08.11.21.29.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Aug 2022 21:29:38 -0700 (PDT) From: Mayuresh Chitale To: Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: Mayuresh Chitale , Atish Patra , Anup Patel , linux-riscv@lists.infradead.org Subject: [RFC PATCH v3 2/2] riscv: mm: use svinval instructions instead of sfence.vma Date: Fri, 12 Aug 2022 09:59:21 +0530 Message-Id: <20220812042921.14508-3-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220812042921.14508-1-mchitale@ventanamicro.com> References: <20220812042921.14508-1-mchitale@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220811_212940_523758_EC711A19 X-CRM114-Status: GOOD ( 15.35 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org When svinval is supported the local_flush_tlb_page* functions would prefer to use the following sequence to optimize the tlb flushes instead of a simple sfence.vma: sfence.w.inval svinval.vma . . svinval.vma sfence.inval.ir The maximum number of consecutive svinval.vma instructions that can be executed in local_flush_tlb_page* functions is limited to PTRS_PER_PTE. This is required to avoid soft lockups and the approach is similar to that used in arm64. Signed-off-by: Mayuresh Chitale --- arch/riscv/mm/tlbflush.c | 108 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 102 insertions(+), 6 deletions(-) diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 27a7db8eb2c4..7d901cf4fec6 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -5,6 +5,14 @@ #include #include #include +#include + +static unsigned long tlb_flush_all_threshold __read_mostly = PTRS_PER_PTE; + +static __always_inline bool has_svinval(void) +{ + return static_branch_unlikely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_SVINVAL]); +} static inline void local_flush_tlb_all_asid(unsigned long asid) { @@ -23,22 +31,110 @@ static inline void local_flush_tlb_page_asid(unsigned long addr, : "memory"); } +static inline void local_sfence_inval_ir(void) +{ + /* + * SFENCE.INVAL.IR + * 0001100 00001 00000 000 00000 1110011 + */ + asm volatile (".word 0x18100073" ::: "memory"); +} + +static inline void local_sfence_w_inval(void) +{ + /* + * SFENCE.W.INVAL + * 0001100 00000 00000 000 00000 1110011 + */ + asm volatile (".word 0x18000073" ::: "memory"); +} + +static inline void local_sinval_vma_asid(unsigned long vma, unsigned long asid) +{ + /* + * rs1 = a0 (VMA) + * rs2 = a1 (asid) + * SINVAL.VMA a0, a1 + * 0001011 01011 01010 000 00000 1110011 + */ + asm volatile ("add a0, %0, zero\n" + "add a1, %1, zero\n" + ".word 0x16B50073\n" + :: "r" (vma), "r" (asid) + : "a0", "a1", "memory"); +} + +static inline void local_sinval_vma(unsigned long vma) +{ + /* + * rs1 = a0 (VMA) + * rs2 = 0 + * SINVAL.VMA a0 + * 0001011 00000 01010 000 00000 1110011 + */ + asm volatile ("add a0, %0, zero\n" + ".word 0x16050073\n" + :: "r" (vma) : "a0", "memory"); +} + static inline void local_flush_tlb_range(unsigned long start, unsigned long size, unsigned long stride) { - if (size <= stride) - local_flush_tlb_page(start); - else + if ((size / stride) <= tlb_flush_all_threshold) { + if (has_svinval()) { + local_sfence_w_inval(); + while (size) { + local_sinval_vma(start); + start += stride; + if (size > stride) + size -= stride; + else + size = 0; + } + local_sfence_inval_ir(); + } else { + while (size) { + local_flush_tlb_page(start); + start += stride; + if (size > stride) + size -= stride; + else + size = 0; + } + } + } else { local_flush_tlb_all(); + } } static inline void local_flush_tlb_range_asid(unsigned long start, unsigned long size, unsigned long stride, unsigned long asid) { - if (size <= stride) - local_flush_tlb_page_asid(start, asid); - else + if ((size / stride) <= tlb_flush_all_threshold) { + if (has_svinval()) { + local_sfence_w_inval(); + while (size) { + local_sinval_vma_asid(start, asid); + start += stride; + if (size > stride) + size -= stride; + else + size = 0; + } + local_sfence_inval_ir(); + } else { + while (size) { + local_flush_tlb_page_asid(start, asid); + start += stride; + if (size > stride) + size -= stride; + else + size = 0; + } + } + } else { local_flush_tlb_all_asid(asid); + } } static void __ipi_flush_tlb_all(void *info)