| Message ID | 20220815050815.22340-8-samuel@sholland.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: Allwinner D1 platform support | expand |
On 15/08/2022 06:08, Samuel Holland wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > "D1 Nezha" is Allwinner's first-party development board for the D1 SoC. > It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard audio, > HDMI, gigabit Ethernet, WiFi and Bluetooth, USB 2.0 host and OTG ports, > plus low-speed I/O from the SoC and a GPIO expander chip. > > Most other D1 boards copied the Nezha's power tree, with the 1.8V rail > powered by the SoCs internal LDOA, analog domains powered by ALDO, and > the rest of the board powered by always-on fixed regulators. Some (but > not all) boards also copied the PWM CPU regulator. To avoid duplication, > factor out the out the regulator references that are common across all > known boards. > > Signed-off-by: Samuel Holland <samuel@sholland.org> Hey Samuel, Replying here as it's the board I happen to have but I saw some kernel panics. Some of this has reproduced for Ron/drmpeg on an unmatched: https://www.w6rz.net/segfault.png but some of this is different: https://gist.github.com/ConchuOD/7d87f574df1ddc56f192e505ecab6574 defconfig is default riscv defconfig - the DRM modules + my cmdline: CONFIG_CMDLINE="earlyprintk=sunxi-uart,0x02500000 earlycon console=ttyS0,115200" lmk if you want anymore info :) Conor. > --- > > arch/riscv/boot/dts/allwinner/Makefile | 1 + > .../sun20i-d1-common-regulators.dtsi | 51 ++++++ > .../boot/dts/allwinner/sun20i-d1-nezha.dts | 171 ++++++++++++++++++ > 3 files changed, 223 insertions(+) > create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi > create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts > > diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile > index f66554cd5c45..b0a15e8c8d82 100644 > --- a/arch/riscv/boot/dts/allwinner/Makefile > +++ b/arch/riscv/boot/dts/allwinner/Makefile > @@ -1 +1,2 @@ > # SPDX-License-Identifier: GPL-2.0 > +dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi > new file mode 100644 > index 000000000000..143a3e710c3c > --- /dev/null > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi > @@ -0,0 +1,51 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> > + > +/ { > + reg_vcc: vcc { > + compatible = "regulator-fixed"; > + regulator-name = "vcc"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + }; > + > + reg_vcc_3v3: vcc-3v3 { > + compatible = "regulator-fixed"; > + regulator-name = "vcc-3v3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + vin-supply = <®_vcc>; > + }; > +}; > + > +&lradc { > + vref-supply = <®_aldo>; > +}; > + > +&pio { > + vcc-pb-supply = <®_vcc_3v3>; > + vcc-pc-supply = <®_vcc_3v3>; > + vcc-pd-supply = <®_vcc_3v3>; > + vcc-pe-supply = <®_vcc_3v3>; > + vcc-pf-supply = <®_vcc_3v3>; > + vcc-pg-supply = <®_vcc_3v3>; > +}; > + > +®_aldo { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + vdd33-supply = <®_vcc_3v3>; > +}; > + > +®_hpldo { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + hpldoin-supply = <®_vcc_3v3>; > +}; > + > +®_ldoa { > + regulator-always-on; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + ldo-in-supply = <®_vcc_3v3>; > +}; > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts > new file mode 100644 > index 000000000000..df865ee15fcf > --- /dev/null > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts > @@ -0,0 +1,171 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> > + > +/dts-v1/; > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/input/input.h> > + > +#include "sun20i-d1.dtsi" > +#include "sun20i-d1-common-regulators.dtsi" > + > +/ { > + model = "Allwinner D1 Nezha"; > + compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1"; > + > + aliases { > + ethernet0 = &emac; > + ethernet1 = &xr829; > + mmc0 = &mmc0; > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + reg_usbvbus: usbvbus { > + compatible = "regulator-fixed"; > + regulator-name = "usbvbus"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */ > + enable-active-high; > + vin-supply = <®_vcc>; > + }; > + > + /* > + * This regulator is PWM-controlled, but the PWM controller is not > + * yet supported, so fix the regulator to its default voltage. > + */ > + reg_vdd_cpu: vdd-cpu { > + compatible = "regulator-fixed"; > + regulator-name = "vdd-cpu"; > + regulator-min-microvolt = <1100000>; > + regulator-max-microvolt = <1100000>; > + vin-supply = <®_vcc>; > + }; > + > + wifi_pwrseq: wifi-pwrseq { > + compatible = "mmc-pwrseq-simple"; > + reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */ > + }; > +}; > + > +&cpu0 { > + cpu-supply = <®_vdd_cpu>; > +}; > + > +&ehci0 { > + status = "okay"; > +}; > + > +&ehci1 { > + status = "okay"; > +}; > + > +&emac { > + pinctrl-0 = <&rgmii_pe_pins>; > + pinctrl-names = "default"; > + phy-handle = <&ext_rgmii_phy>; > + phy-mode = "rgmii-id"; > + phy-supply = <®_vcc_3v3>; > + status = "okay"; > +}; > + > +&i2c2 { > + pinctrl-0 = <&i2c2_pb0_pins>; > + pinctrl-names = "default"; > + status = "okay"; > + > + pcf8574a: gpio@38 { > + compatible = "nxp,pcf8574a"; > + reg = <0x38>; > + interrupt-parent = <&pio>; > + interrupts = <1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */ > + interrupt-controller; > + gpio-controller; > + #gpio-cells = <2>; > + #interrupt-cells = <2>; > + }; > +}; > + > +&lradc { > + status = "okay"; > + > + button-160 { > + label = "OK"; > + linux,code = <KEY_OK>; > + channel = <0>; > + voltage = <160000>; > + }; > +}; > + > +&mdio { > + ext_rgmii_phy: ethernet-phy@1 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <1>; > + }; > +}; > + > +&mmc0 { > + bus-width = <4>; > + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ > + disable-wp; > + vmmc-supply = <®_vcc_3v3>; > + vqmmc-supply = <®_vcc_3v3>; > + pinctrl-0 = <&mmc0_pins>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > + > +&mmc1 { > + bus-width = <4>; > + mmc-pwrseq = <&wifi_pwrseq>; > + non-removable; > + vmmc-supply = <®_vcc_3v3>; > + vqmmc-supply = <®_vcc_3v3>; > + pinctrl-0 = <&mmc1_pins>; > + pinctrl-names = "default"; > + status = "okay"; > + > + xr829: wifi@1 { > + reg = <1>; > + }; > +}; > + > +&ohci0 { > + status = "okay"; > +}; > + > +&ohci1 { > + status = "okay"; > +}; > + > +&uart0 { > + pinctrl-0 = <&uart0_pb8_pins>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > + > +&uart1 { > + uart-has-rtscts; > + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>; > + pinctrl-names = "default"; > + status = "okay"; > + > + /* XR829 bluetooth is connected here */ > +}; > + > +&usb_otg { > + dr_mode = "otg"; > + status = "okay"; > +}; > + > +&usbphy { > + usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */ > + usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ > + usb0_vbus-supply = <®_usbvbus>; > + usb1_vbus-supply = <®_vcc>; > + status = "okay"; > +}; > -- > 2.35.1 >
On 15/08/2022 18:37, Conor Dooley - M52691 wrote: > On 15/08/2022 06:08, Samuel Holland wrote: >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >> >> "D1 Nezha" is Allwinner's first-party development board for the D1 SoC. >> It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard audio, >> HDMI, gigabit Ethernet, WiFi and Bluetooth, USB 2.0 host and OTG ports, >> plus low-speed I/O from the SoC and a GPIO expander chip. >> >> Most other D1 boards copied the Nezha's power tree, with the 1.8V rail >> powered by the SoCs internal LDOA, analog domains powered by ALDO, and >> the rest of the board powered by always-on fixed regulators. Some (but >> not all) boards also copied the PWM CPU regulator. To avoid duplication, >> factor out the out the regulator references that are common across all >> known boards. >> >> Signed-off-by: Samuel Holland <samuel@sholland.org> > > Hey Samuel, > Replying here as it's the board I happen to have but I saw some kernel > panics. Some of this has reproduced for Ron/drmpeg on an unmatched: > https://www.w6rz.net/segfault.png > but some of this is different: > https://gist.github.com/ConchuOD/7d87f574df1ddc56f192e505ecab6574 > > defconfig is default riscv defconfig - the DRM modules + my cmdline: > CONFIG_CMDLINE="earlyprintk=sunxi-uart,0x02500000 earlycon console=ttyS0,115200" I seem to be making a hames of things today. Started it with the email to the wrong patchset this morning and now here I am 12h later and I am messing up my stuff here too :/ I think I confused myself with the configs & logs. This one here was the default defconfig + CONFIG_CMDLINE [0]: https://gist.github.com/ConchuOD/7d87f574df1ddc56f192e505ecab6574#file-log-txt-no-drm This one was from the d1-wip branch that I had been using prior to the patchset with CONFIG_CMDLINE [0]: https://gist.github.com/ConchuOD/7d87f574df1ddc56f192e505ecab6574#file-log-txt-with-drm And with a defconfig from Heiko I get hangs where output dies using CONFIG_CMDLINE [1]: https://paste.debian.net/1250519/ https://gist.github.com/ConchuOD/7d87f574df1ddc56f192e505ecab6574#file-heiko-config For all of the above I have used: 0 - CONFIG_CMDLINE="root=/dev/nfs ip=dhcp nfsroot=192.168.2.5:/stuff/nfs_share earlyprintk=sunxi-uart,0x02500000 earlycon console=ttyS0,115200" 1 - CONFIG_CMDLINE="earlyprintk=sunxi-uart,0x02500000 earlycon console=ttyS0,115200" If I don't use [1], I don't get any output on the uart my u-boot uses. Heiko reminded me that the D1 needs the memory nodes from the dts etc, so it's actually using the u-boot dts. Did you make breaking changes between what worked with the d1-wip branch and this submission? I'll update what my u-boot has, but in the meantime hopefully this makes things a little clearer. Sorry for all the noise etc, I seem to be all over the shop today. Conor. > > lmk if you want anymore info :) > Conor. > >> --- >> >> arch/riscv/boot/dts/allwinner/Makefile | 1 + >> .../sun20i-d1-common-regulators.dtsi | 51 ++++++ >> .../boot/dts/allwinner/sun20i-d1-nezha.dts | 171 ++++++++++++++++++ >> 3 files changed, 223 insertions(+) >> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi >> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts >> >> diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile >> index f66554cd5c45..b0a15e8c8d82 100644 >> --- a/arch/riscv/boot/dts/allwinner/Makefile >> +++ b/arch/riscv/boot/dts/allwinner/Makefile >> @@ -1 +1,2 @@ >> # SPDX-License-Identifier: GPL-2.0 >> +dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb >> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi >> new file mode 100644 >> index 000000000000..143a3e710c3c >> --- /dev/null >> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi >> @@ -0,0 +1,51 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ or MIT) >> +// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> >> + >> +/ { >> + reg_vcc: vcc { >> + compatible = "regulator-fixed"; >> + regulator-name = "vcc"; >> + regulator-min-microvolt = <5000000>; >> + regulator-max-microvolt = <5000000>; >> + }; >> + >> + reg_vcc_3v3: vcc-3v3 { >> + compatible = "regulator-fixed"; >> + regulator-name = "vcc-3v3"; >> + regulator-min-microvolt = <3300000>; >> + regulator-max-microvolt = <3300000>; >> + vin-supply = <®_vcc>; >> + }; >> +}; >> + >> +&lradc { >> + vref-supply = <®_aldo>; >> +}; >> + >> +&pio { >> + vcc-pb-supply = <®_vcc_3v3>; >> + vcc-pc-supply = <®_vcc_3v3>; >> + vcc-pd-supply = <®_vcc_3v3>; >> + vcc-pe-supply = <®_vcc_3v3>; >> + vcc-pf-supply = <®_vcc_3v3>; >> + vcc-pg-supply = <®_vcc_3v3>; >> +}; >> + >> +®_aldo { >> + regulator-min-microvolt = <1800000>; >> + regulator-max-microvolt = <1800000>; >> + vdd33-supply = <®_vcc_3v3>; >> +}; >> + >> +®_hpldo { >> + regulator-min-microvolt = <1800000>; >> + regulator-max-microvolt = <1800000>; >> + hpldoin-supply = <®_vcc_3v3>; >> +}; >> + >> +®_ldoa { >> + regulator-always-on; >> + regulator-min-microvolt = <1800000>; >> + regulator-max-microvolt = <1800000>; >> + ldo-in-supply = <®_vcc_3v3>; >> +}; >> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts >> new file mode 100644 >> index 000000000000..df865ee15fcf >> --- /dev/null >> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts >> @@ -0,0 +1,171 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ or MIT) >> +// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> >> + >> +/dts-v1/; >> + >> +#include <dt-bindings/gpio/gpio.h> >> +#include <dt-bindings/input/input.h> >> + >> +#include "sun20i-d1.dtsi" >> +#include "sun20i-d1-common-regulators.dtsi" >> + >> +/ { >> + model = "Allwinner D1 Nezha"; >> + compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1"; >> + >> + aliases { >> + ethernet0 = &emac; >> + ethernet1 = &xr829; >> + mmc0 = &mmc0; >> + serial0 = &uart0; >> + }; >> + >> + chosen { >> + stdout-path = "serial0:115200n8"; >> + }; >> + >> + reg_usbvbus: usbvbus { >> + compatible = "regulator-fixed"; >> + regulator-name = "usbvbus"; >> + regulator-min-microvolt = <5000000>; >> + regulator-max-microvolt = <5000000>; >> + gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */ >> + enable-active-high; >> + vin-supply = <®_vcc>; >> + }; >> + >> + /* >> + * This regulator is PWM-controlled, but the PWM controller is not >> + * yet supported, so fix the regulator to its default voltage. >> + */ >> + reg_vdd_cpu: vdd-cpu { >> + compatible = "regulator-fixed"; >> + regulator-name = "vdd-cpu"; >> + regulator-min-microvolt = <1100000>; >> + regulator-max-microvolt = <1100000>; >> + vin-supply = <®_vcc>; >> + }; >> + >> + wifi_pwrseq: wifi-pwrseq { >> + compatible = "mmc-pwrseq-simple"; >> + reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */ >> + }; >> +}; >> + >> +&cpu0 { >> + cpu-supply = <®_vdd_cpu>; >> +}; >> + >> +&ehci0 { >> + status = "okay"; >> +}; >> + >> +&ehci1 { >> + status = "okay"; >> +}; >> + >> +&emac { >> + pinctrl-0 = <&rgmii_pe_pins>; >> + pinctrl-names = "default"; >> + phy-handle = <&ext_rgmii_phy>; >> + phy-mode = "rgmii-id"; >> + phy-supply = <®_vcc_3v3>; >> + status = "okay"; >> +}; >> + >> +&i2c2 { >> + pinctrl-0 = <&i2c2_pb0_pins>; >> + pinctrl-names = "default"; >> + status = "okay"; >> + >> + pcf8574a: gpio@38 { >> + compatible = "nxp,pcf8574a"; >> + reg = <0x38>; >> + interrupt-parent = <&pio>; >> + interrupts = <1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */ >> + interrupt-controller; >> + gpio-controller; >> + #gpio-cells = <2>; >> + #interrupt-cells = <2>; >> + }; >> +}; >> + >> +&lradc { >> + status = "okay"; >> + >> + button-160 { >> + label = "OK"; >> + linux,code = <KEY_OK>; >> + channel = <0>; >> + voltage = <160000>; >> + }; >> +}; >> + >> +&mdio { >> + ext_rgmii_phy: ethernet-phy@1 { >> + compatible = "ethernet-phy-ieee802.3-c22"; >> + reg = <1>; >> + }; >> +}; >> + >> +&mmc0 { >> + bus-width = <4>; >> + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ >> + disable-wp; >> + vmmc-supply = <®_vcc_3v3>; >> + vqmmc-supply = <®_vcc_3v3>; >> + pinctrl-0 = <&mmc0_pins>; >> + pinctrl-names = "default"; >> + status = "okay"; >> +}; >> + >> +&mmc1 { >> + bus-width = <4>; >> + mmc-pwrseq = <&wifi_pwrseq>; >> + non-removable; >> + vmmc-supply = <®_vcc_3v3>; >> + vqmmc-supply = <®_vcc_3v3>; >> + pinctrl-0 = <&mmc1_pins>; >> + pinctrl-names = "default"; >> + status = "okay"; >> + >> + xr829: wifi@1 { >> + reg = <1>; >> + }; >> +}; >> + >> +&ohci0 { >> + status = "okay"; >> +}; >> + >> +&ohci1 { >> + status = "okay"; >> +}; >> + >> +&uart0 { >> + pinctrl-0 = <&uart0_pb8_pins>; >> + pinctrl-names = "default"; >> + status = "okay"; >> +}; >> + >> +&uart1 { >> + uart-has-rtscts; >> + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>; >> + pinctrl-names = "default"; >> + status = "okay"; >> + >> + /* XR829 bluetooth is connected here */ >> +}; >> + >> +&usb_otg { >> + dr_mode = "otg"; >> + status = "okay"; >> +}; >> + >> +&usbphy { >> + usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */ >> + usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ >> + usb0_vbus-supply = <®_usbvbus>; >> + usb1_vbus-supply = <®_vcc>; >> + status = "okay"; >> +}; >> -- >> 2.35.1 >> >
Am Montag, 15. August 2022, 07:08:10 CEST schrieb Samuel Holland: > "D1 Nezha" is Allwinner's first-party development board for the D1 SoC. > It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard audio, > HDMI, gigabit Ethernet, WiFi and Bluetooth, USB 2.0 host and OTG ports, > plus low-speed I/O from the SoC and a GPIO expander chip. > > Most other D1 boards copied the Nezha's power tree, with the 1.8V rail > powered by the SoCs internal LDOA, analog domains powered by ALDO, and > the rest of the board powered by always-on fixed regulators. Some (but > not all) boards also copied the PWM CPU regulator. To avoid duplication, > factor out the out the regulator references that are common across all > known boards. > > Signed-off-by: Samuel Holland <samuel@sholland.org> > --- > > arch/riscv/boot/dts/allwinner/Makefile | 1 + > .../sun20i-d1-common-regulators.dtsi | 51 ++++++ > .../boot/dts/allwinner/sun20i-d1-nezha.dts | 171 ++++++++++++++++++ > 3 files changed, 223 insertions(+) > create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi > create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts > > diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile > index f66554cd5c45..b0a15e8c8d82 100644 > --- a/arch/riscv/boot/dts/allwinner/Makefile > +++ b/arch/riscv/boot/dts/allwinner/Makefile > @@ -1 +1,2 @@ > # SPDX-License-Identifier: GPL-2.0 > +dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi > new file mode 100644 > index 000000000000..143a3e710c3c > --- /dev/null > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi > @@ -0,0 +1,51 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> in (most/all) other devicetrees this is looks more like // SPDX-License-Identifier: (GPL-2.0+ or MIT) /* Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> */ otherwise Tested-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Hey Samuel, Finally got around to giving this a go with the fix for loading modules which is mostly what was blocking me before.. On 15/08/2022 06:08, Samuel Holland wrote: > "D1 Nezha" is Allwinner's first-party development board for the D1 SoC. > It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard audio, I am really not keen on the way you have things, with the memory nodes removed from the device tree. I know your preferred flow for booting these things might be to pass the dtb up from U-Boot, but I think the devicetree in the kernel should be usable in a standalone manner, even if that is the barest-minimum memory config. I did figure out all of my issues getting booted, thanks partly to Heiko. The U-Boot dtb being misaligned was part of it as was my initramfs with some stale sunxi modules in it causing RCU stalls.. so sorry for the noise on that front (and thanks again to Heiko!). Modulo the memory node, since I had to hack that in to get things working & I do not want to have to keep doing: Tested-by: Conor Dooley <conor.dooley@microchip.com> Thanks & apologies again for the modules-related issues - it was hard to debug that one since module loading was broken on RISC-V at the time. Conor. > HDMI, gigabit Ethernet, WiFi and Bluetooth, USB 2.0 host and OTG ports, > plus low-speed I/O from the SoC and a GPIO expander chip. > > Most other D1 boards copied the Nezha's power tree, with the 1.8V rail > powered by the SoCs internal LDOA, analog domains powered by ALDO, and > the rest of the board powered by always-on fixed regulators. Some (but > not all) boards also copied the PWM CPU regulator. To avoid duplication, > factor out the out the regulator references that are common across all > known boards. > > Signed-off-by: Samuel Holland <samuel@sholland.org> > --- > > arch/riscv/boot/dts/allwinner/Makefile | 1 + > .../sun20i-d1-common-regulators.dtsi | 51 ++++++ > .../boot/dts/allwinner/sun20i-d1-nezha.dts | 171 ++++++++++++++++++ > 3 files changed, 223 insertions(+) > create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi > create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts > > diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile > index f66554cd5c45..b0a15e8c8d82 100644 > --- a/arch/riscv/boot/dts/allwinner/Makefile > +++ b/arch/riscv/boot/dts/allwinner/Makefile > @@ -1 +1,2 @@ > # SPDX-License-Identifier: GPL-2.0 > +dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi > new file mode 100644 > index 000000000000..143a3e710c3c > --- /dev/null > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi > @@ -0,0 +1,51 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> > + > +/ { > + reg_vcc: vcc { > + compatible = "regulator-fixed"; > + regulator-name = "vcc"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + }; > + > + reg_vcc_3v3: vcc-3v3 { > + compatible = "regulator-fixed"; > + regulator-name = "vcc-3v3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + vin-supply = <®_vcc>; > + }; > +}; > + > +&lradc { > + vref-supply = <®_aldo>; > +}; > + > +&pio { > + vcc-pb-supply = <®_vcc_3v3>; > + vcc-pc-supply = <®_vcc_3v3>; > + vcc-pd-supply = <®_vcc_3v3>; > + vcc-pe-supply = <®_vcc_3v3>; > + vcc-pf-supply = <®_vcc_3v3>; > + vcc-pg-supply = <®_vcc_3v3>; > +}; > + > +®_aldo { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + vdd33-supply = <®_vcc_3v3>; > +}; > + > +®_hpldo { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + hpldoin-supply = <®_vcc_3v3>; > +}; > + > +®_ldoa { > + regulator-always-on; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + ldo-in-supply = <®_vcc_3v3>; > +}; > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts > new file mode 100644 > index 000000000000..df865ee15fcf > --- /dev/null > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts > @@ -0,0 +1,171 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> > + > +/dts-v1/; > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/input/input.h> > + > +#include "sun20i-d1.dtsi" > +#include "sun20i-d1-common-regulators.dtsi" > + > +/ { > + model = "Allwinner D1 Nezha"; > + compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1"; > + > + aliases { > + ethernet0 = &emac; > + ethernet1 = &xr829; > + mmc0 = &mmc0; > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + reg_usbvbus: usbvbus { > + compatible = "regulator-fixed"; > + regulator-name = "usbvbus"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */ > + enable-active-high; > + vin-supply = <®_vcc>; > + }; > + > + /* > + * This regulator is PWM-controlled, but the PWM controller is not > + * yet supported, so fix the regulator to its default voltage. > + */ > + reg_vdd_cpu: vdd-cpu { > + compatible = "regulator-fixed"; > + regulator-name = "vdd-cpu"; > + regulator-min-microvolt = <1100000>; > + regulator-max-microvolt = <1100000>; > + vin-supply = <®_vcc>; > + }; > + > + wifi_pwrseq: wifi-pwrseq { > + compatible = "mmc-pwrseq-simple"; > + reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */ > + }; > +}; > + > +&cpu0 { > + cpu-supply = <®_vdd_cpu>; > +}; > + > +&ehci0 { > + status = "okay"; > +}; > + > +&ehci1 { > + status = "okay"; > +}; > + > +&emac { > + pinctrl-0 = <&rgmii_pe_pins>; > + pinctrl-names = "default"; > + phy-handle = <&ext_rgmii_phy>; > + phy-mode = "rgmii-id"; > + phy-supply = <®_vcc_3v3>; > + status = "okay"; > +}; > + > +&i2c2 { > + pinctrl-0 = <&i2c2_pb0_pins>; > + pinctrl-names = "default"; > + status = "okay"; > + > + pcf8574a: gpio@38 { > + compatible = "nxp,pcf8574a"; > + reg = <0x38>; > + interrupt-parent = <&pio>; > + interrupts = <1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */ > + interrupt-controller; > + gpio-controller; > + #gpio-cells = <2>; > + #interrupt-cells = <2>; > + }; > +}; > + > +&lradc { > + status = "okay"; > + > + button-160 { > + label = "OK"; > + linux,code = <KEY_OK>; > + channel = <0>; > + voltage = <160000>; > + }; > +}; > + > +&mdio { > + ext_rgmii_phy: ethernet-phy@1 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <1>; > + }; > +}; > + > +&mmc0 { > + bus-width = <4>; > + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ > + disable-wp; > + vmmc-supply = <®_vcc_3v3>; > + vqmmc-supply = <®_vcc_3v3>; > + pinctrl-0 = <&mmc0_pins>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > + > +&mmc1 { > + bus-width = <4>; > + mmc-pwrseq = <&wifi_pwrseq>; > + non-removable; > + vmmc-supply = <®_vcc_3v3>; > + vqmmc-supply = <®_vcc_3v3>; > + pinctrl-0 = <&mmc1_pins>; > + pinctrl-names = "default"; > + status = "okay"; > + > + xr829: wifi@1 { > + reg = <1>; > + }; > +}; > + > +&ohci0 { > + status = "okay"; > +}; > + > +&ohci1 { > + status = "okay"; > +}; > + > +&uart0 { > + pinctrl-0 = <&uart0_pb8_pins>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > + > +&uart1 { > + uart-has-rtscts; > + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>; > + pinctrl-names = "default"; > + status = "okay"; > + > + /* XR829 bluetooth is connected here */ > +}; > + > +&usb_otg { > + dr_mode = "otg"; > + status = "okay"; > +}; > + > +&usbphy { > + usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */ > + usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ > + usb0_vbus-supply = <®_usbvbus>; > + usb1_vbus-supply = <®_vcc>; > + status = "okay"; > +};
在 2022-08-19星期五的 22:10 +0000，Conor.Dooley@microchip.com写道： > Hey Samuel, > > Finally got around to giving this a go with the fix for loading > modules which is mostly what was blocking me before.. > > On 15/08/2022 06:08, Samuel Holland wrote: > > "D1 Nezha" is Allwinner's first-party development board for the D1 > > SoC. > > It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard > > audio, BTW I assume 512MB version is never publicly available, it's only some early samples that have the circuit of one of the DDR chips broken. > > I am really not keen on the way you have things, with the memory > nodes removed from the device tree. I know your preferred flow > for booting these things might be to pass the dtb up from U-Boot, > but I think the devicetree in the kernel should be usable in a > standalone manner, even if that is the barest-minimum memory > config. W/o interception of BL, I think there're more complex situations of the memory, e.g. some part of the memory is reserved. > > I did figure out all of my issues getting booted, thanks partly > to Heiko. The U-Boot dtb being misaligned was part of it as was > my initramfs with some stale sunxi modules in it causing RCU > stalls.. so sorry for the noise on that front (and thanks again > to Heiko!). > > Modulo the memory node, since I had to hack that in to get things > working & I do not want to have to keep doing: > Tested-by: Conor Dooley <conor.dooley@microchip.com> > > Thanks & apologies again for the modules-related issues - it was > hard to debug that one since module loading was broken on RISC-V > at the time. > Conor. > > > HDMI, gigabit Ethernet, WiFi and Bluetooth, USB 2.0 host and OTG > > ports, > > plus low-speed I/O from the SoC and a GPIO expander chip. > > > > Most other D1 boards copied the Nezha's power tree, with the 1.8V > > rail > > powered by the SoCs internal LDOA, analog domains powered by ALDO, > > and > > the rest of the board powered by always-on fixed regulators. Some > > (but > > not all) boards also copied the PWM CPU regulator. To avoid > > duplication, > > factor out the out the regulator references that are common across > > all > > known boards. > > > > Signed-off-by: Samuel Holland <samuel@sholland.org> > > --- > > > > arch/riscv/boot/dts/allwinner/Makefile | 1 + > > .../sun20i-d1-common-regulators.dtsi | 51 ++++++ > > .../boot/dts/allwinner/sun20i-d1-nezha.dts | 171 > > ++++++++++++++++++ > > 3 files changed, 223 insertions(+) > > create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-common- > > regulators.dtsi > > create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1- > > nezha.dts > > > > diff --git a/arch/riscv/boot/dts/allwinner/Makefile > > b/arch/riscv/boot/dts/allwinner/Makefile > > index f66554cd5c45..b0a15e8c8d82 100644 > > --- a/arch/riscv/boot/dts/allwinner/Makefile > > +++ b/arch/riscv/boot/dts/allwinner/Makefile > > @@ -1 +1,2 @@ > > # SPDX-License-Identifier: GPL-2.0 > > +dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb > > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-common- > > regulators.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1-common- > > regulators.dtsi > > new file mode 100644 > > index 000000000000..143a3e710c3c > > --- /dev/null > > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-common- > > regulators.dtsi > > @@ -0,0 +1,51 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > > +// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> > > + > > +/ { > > + reg_vcc: vcc { > > + compatible = "regulator-fixed"; > > + regulator-name = "vcc"; > > + regulator-min-microvolt = <5000000>; > > + regulator-max-microvolt = <5000000>; > > + }; > > + > > + reg_vcc_3v3: vcc-3v3 { > > + compatible = "regulator-fixed"; > > + regulator-name = "vcc-3v3"; > > + regulator-min-microvolt = <3300000>; > > + regulator-max-microvolt = <3300000>; > > + vin-supply = <®_vcc>; > > + }; > > +}; > > + > > +&lradc { > > + vref-supply = <®_aldo>; > > +}; > > + > > +&pio { > > + vcc-pb-supply = <®_vcc_3v3>; > > + vcc-pc-supply = <®_vcc_3v3>; > > + vcc-pd-supply = <®_vcc_3v3>; > > + vcc-pe-supply = <®_vcc_3v3>; > > + vcc-pf-supply = <®_vcc_3v3>; > > + vcc-pg-supply = <®_vcc_3v3>; > > +}; > > + > > +®_aldo { > > + regulator-min-microvolt = <1800000>; > > + regulator-max-microvolt = <1800000>; > > + vdd33-supply = <®_vcc_3v3>; > > +}; > > + > > +®_hpldo { > > + regulator-min-microvolt = <1800000>; > > + regulator-max-microvolt = <1800000>; > > + hpldoin-supply = <®_vcc_3v3>; > > +}; > > + > > +®_ldoa { > > + regulator-always-on; > > + regulator-min-microvolt = <1800000>; > > + regulator-max-microvolt = <1800000>; > > + ldo-in-supply = <®_vcc_3v3>; > > +}; > > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts > > b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts > > new file mode 100644 > > index 000000000000..df865ee15fcf > > --- /dev/null > > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts > > @@ -0,0 +1,171 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > > +// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> > > + > > +/dts-v1/; > > + > > +#include <dt-bindings/gpio/gpio.h> > > +#include <dt-bindings/input/input.h> > > + > > +#include "sun20i-d1.dtsi" > > +#include "sun20i-d1-common-regulators.dtsi" > > + > > +/ { > > + model = "Allwinner D1 Nezha"; > > + compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1"; > > + > > + aliases { > > + ethernet0 = &emac; > > + ethernet1 = &xr829; > > + mmc0 = &mmc0; > > + serial0 = &uart0; > > + }; > > + > > + chosen { > > + stdout-path = "serial0:115200n8"; > > + }; > > + > > + reg_usbvbus: usbvbus { > > + compatible = "regulator-fixed"; > > + regulator-name = "usbvbus"; > > + regulator-min-microvolt = <5000000>; > > + regulator-max-microvolt = <5000000>; > > + gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */ > > + enable-active-high; > > + vin-supply = <®_vcc>; > > + }; > > + > > + /* > > + * This regulator is PWM-controlled, but the PWM controller > > is not > > + * yet supported, so fix the regulator to its default > > voltage. > > + */ > > + reg_vdd_cpu: vdd-cpu { > > + compatible = "regulator-fixed"; > > + regulator-name = "vdd-cpu"; > > + regulator-min-microvolt = <1100000>; > > + regulator-max-microvolt = <1100000>; > > + vin-supply = <®_vcc>; > > + }; > > + > > + wifi_pwrseq: wifi-pwrseq { > > + compatible = "mmc-pwrseq-simple"; > > + reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 > > */ > > + }; > > +}; > > + > > +&cpu0 { > > + cpu-supply = <®_vdd_cpu>; > > +}; > > + > > +&ehci0 { > > + status = "okay"; > > +}; > > + > > +&ehci1 { > > + status = "okay"; > > +}; > > + > > +&emac { > > + pinctrl-0 = <&rgmii_pe_pins>; > > + pinctrl-names = "default"; > > + phy-handle = <&ext_rgmii_phy>; > > + phy-mode = "rgmii-id"; > > + phy-supply = <®_vcc_3v3>; > > + status = "okay"; > > +}; > > + > > +&i2c2 { > > + pinctrl-0 = <&i2c2_pb0_pins>; > > + pinctrl-names = "default"; > > + status = "okay"; > > + > > + pcf8574a: gpio@38 { > > + compatible = "nxp,pcf8574a"; > > + reg = <0x38>; > > + interrupt-parent = <&pio>; > > + interrupts = <1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */ > > + interrupt-controller; > > + gpio-controller; > > + #gpio-cells = <2>; > > + #interrupt-cells = <2>; > > + }; > > +}; > > + > > +&lradc { > > + status = "okay"; > > + > > + button-160 { > > + label = "OK"; > > + linux,code = <KEY_OK>; > > + channel = <0>; > > + voltage = <160000>; > > + }; > > +}; > > + > > +&mdio { > > + ext_rgmii_phy: ethernet-phy@1 { > > + compatible = "ethernet-phy-ieee802.3-c22"; > > + reg = <1>; > > + }; > > +}; > > + > > +&mmc0 { > > + bus-width = <4>; > > + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ > > + disable-wp; > > + vmmc-supply = <®_vcc_3v3>; > > + vqmmc-supply = <®_vcc_3v3>; > > + pinctrl-0 = <&mmc0_pins>; > > + pinctrl-names = "default"; > > + status = "okay"; > > +}; > > + > > +&mmc1 { > > + bus-width = <4>; > > + mmc-pwrseq = <&wifi_pwrseq>; > > + non-removable; > > + vmmc-supply = <®_vcc_3v3>; > > + vqmmc-supply = <®_vcc_3v3>; > > + pinctrl-0 = <&mmc1_pins>; > > + pinctrl-names = "default"; > > + status = "okay"; > > + > > + xr829: wifi@1 { > > + reg = <1>; > > + }; > > +}; > > + > > +&ohci0 { > > + status = "okay"; > > +}; > > + > > +&ohci1 { > > + status = "okay"; > > +}; > > + > > +&uart0 { > > + pinctrl-0 = <&uart0_pb8_pins>; > > + pinctrl-names = "default"; > > + status = "okay"; > > +}; > > + > > +&uart1 { > > + uart-has-rtscts; > > + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>; > > + pinctrl-names = "default"; > > + status = "okay"; > > + > > + /* XR829 bluetooth is connected here */ > > +}; > > + > > +&usb_otg { > > + dr_mode = "otg"; > > + status = "okay"; > > +}; > > + > > +&usbphy { > > + usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 > > */ > > + usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 > > */ > > + usb0_vbus-supply = <®_usbvbus>; > > + usb1_vbus-supply = <®_vcc>; > > + status = "okay"; > > +};
>>>>> "Samuel" == Samuel Holland <samuel@sholland.org> writes: > "D1 Nezha" is Allwinner's first-party development board for the D1 SoC. > It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard audio, > HDMI, gigabit Ethernet, WiFi and Bluetooth, USB 2.0 host and OTG ports, > plus low-speed I/O from the SoC and a GPIO expander chip. > Most other D1 boards copied the Nezha's power tree, with the 1.8V rail > powered by the SoCs internal LDOA, analog domains powered by ALDO, and > the rest of the board powered by always-on fixed regulators. Some (but > not all) boards also copied the PWM CPU regulator. To avoid duplication, > factor out the out the regulator references that are common across all NIT: s/out the out the/out the/
>>>>> <Conor.Dooley@microchip.com> writes: > Hey Samuel, > Finally got around to giving this a go with the fix for loading > modules which is mostly what was blocking me before.. > On 15/08/2022 06:08, Samuel Holland wrote: >> "D1 Nezha" is Allwinner's first-party development board for the D1 SoC. >> It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard audio, > I am really not keen on the way you have things, with the memory > nodes removed from the device tree. I know your preferred flow > for booting these things might be to pass the dtb up from U-Boot, > but I think the devicetree in the kernel should be usable in a > standalone manner, even if that is the barest-minimum memory > config. Yes, this also confused me. Part of the reason seems to be that u-boot on RISC-V doesn't fixup the memory node of a provided device tree like it is done on E.G. ARM for some reason.
Hi Conor, On 8/19/22 5:10 PM, Conor.Dooley@microchip.com wrote: > Finally got around to giving this a go with the fix for loading > modules which is mostly what was blocking me before.. > > On 15/08/2022 06:08, Samuel Holland wrote: >> "D1 Nezha" is Allwinner's first-party development board for the D1 SoC. >> It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard audio, > > I am really not keen on the way you have things, with the memory > nodes removed from the device tree. I know your preferred flow > for booting these things might be to pass the dtb up from U-Boot, > but I think the devicetree in the kernel should be usable in a > standalone manner, even if that is the barest-minimum memory > config. That is simply not possible to guarantee. As an obvious example, consider the MangoPi MQ-Pro board with socketed DRAM: https://twitter.com/mangopi_sbc/status/1516225559214583808 But focusing on the /memory node misses the bigger picture. The DTB is passed through _all_ of the firmware stages, and gets patched by every one of them: - SPL/boot0 adds the /memory node with the detected DRAM size. If the in-tree DTS has a "minimum memory config" (which for a board with socketed DRAM means the smallest possible die), I guarantee people will use it and complain about missing DRAM. - The SBI implementation reserves memory for itself and any possible secure partitions. Right now, booting happens to work without the reserved-memory node because the SBI implementation is loaded at the beginning of RAM, and Linux ignores RAM below the kernel load address. However, memory-constrained devices (e.g. D1s) will need to get those 2 MiB back by loading the kernel at the start of DRAM and SBI at the end of DRAM. Then the reserved-memory node becomes quite important. It also adds nodes for CPU idle states, since the available states and their latencies depend on the SBI implementation. It also reserves devices used by it or by a secure partition. And it is responsible for extracting data (e.g. MAC addresses) from "secure" eFuses which the OS may not have access to. - U-Boot adds other information, like boot arguments, the address of the initramfs and framebuffer, etc. These are less of a concern because of course U-Boot can patch these in to a DTB loaded from disk, but they are relevant if you want to load a DTB from a later bootloader like GRUB. If you load a DTB from disk, you lose all of the changes made by the earlier firmware stages. On ARM, U-Boot tries to work around this by copying a few specific bits of information from the firmware DTB to the DTB loaded from disk. But this misses the point that the SBI implementation can modify *any* part of the DTB. (So in practice U-Boot on ARM already loses CPU idle states and reserved memory nodes that were added by the PSCI implementation.) As an extreme example, consider paravirtualization, where only a small subset of DRAM and peripherals may be made available to any one OS partition. Fundamentally, I reserve the right to make arbitrary changes to the DTB in the SBI implementation, and thus I cannot condone using the DTBs generated from the Linux source tree for any purpose other than validation. Regards, Samuel
On 09/09/2022 05:37, Samuel Holland wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you > know the content is safe > > Hi Conor, > > On 8/19/22 5:10 PM, Conor.Dooley@microchip.com wrote: >> Finally got around to giving this a go with the fix for loading >> modules which is mostly what was blocking me before.. >> >> On 15/08/2022 06:08, Samuel Holland wrote: >>> "D1 Nezha" is Allwinner's first-party development board for the >>> D1 SoC. It was shipped with 512M, 1G, or 2G of DDR3. It supports >>> onboard audio, >> >> I am really not keen on the way you have things, with the memory >> nodes removed from the device tree. I know your preferred flow for >> booting these things might be to pass the dtb up from U-Boot, but I >> think the devicetree in the kernel should be usable in a standalone >> manner, even if that is the barest-minimum memory config. > > That is simply not possible to guarantee. As an obvious example, > consider the MangoPi MQ-Pro board with socketed DRAM: Yeah, I knew in my heart-of-hearts that this probably was a non runner. > > https://twitter.com/mangopi_sbc/status/1516225559214583808 > > But focusing on the /memory node misses the bigger picture. The DTB > is passed through _all_ of the firmware stages, and gets patched by > every one of them: > > - SPL/boot0 adds the /memory node with the detected DRAM size. If the > in-tree DTS has a "minimum memory config" (which for a board with > socketed DRAM means the smallest possible die), I guarantee people > will use it and complain about missing DRAM. True, but they are also complaining about missing DRAM as is ;) No possibility of winning here unfortunately. > - The SBI implementation reserves memory for itself and any possible > secure partitions. Right now, booting happens to work without the > reserved-memory node because the SBI implementation is loaded at the > beginning of RAM, and Linux ignores RAM below the kernel load > address. Surely this sort of thing is a common problem though, it's not like any of us are doing something unique here are we? At least if there was a arch wide policy about the validity of the upstream DTS in the face of the SBI etc inflicting changes there'd be something to point to. I am just looking at this from a "everyone else has a usable dts in the kernel, but the D1 boards wont have" point of view. > However, memory-constrained devices (e.g. D1s) will need to get those > 2 MiB back by loading the kernel at the start of DRAM and SBI at the > end of DRAM. Then the reserved-memory node becomes quite important. > > It also adds nodes for CPU idle states, since the available states > and their latencies depend on the SBI implementation. > > It also reserves devices used by it or by a secure partition. And it > is responsible for extracting data (e.g. MAC addresses) from "secure" > eFuses which the OS may not have access to. > > - U-Boot adds other information, like boot arguments, the address of > the initramfs and framebuffer, etc. These are less of a concern > because of course U-Boot can patch these in to a DTB loaded from > disk, but they are relevant if you want to load a DTB from a later > bootloader like GRUB. > > If you load a DTB from disk, you lose all of the changes made by the > earlier firmware stages. On ARM, U-Boot tries to work around this by > copying a few specific bits of information from the firmware DTB to > the DTB loaded from disk. But this misses the point that the SBI > implementation can modify *any* part of the DTB. (So in practice > U-Boot on ARM already loses CPU idle states and reserved memory nodes > that were added by the PSCI implementation.) All of these things are valid, but they are reasons why your flow in your bootloaders etc are the way they are more than a reason why the upstream dts will not work for someone who is not interested in that flow. At the end of the day, I only care so much about this as it is not me that has to deal with any confusion from either approach. I'll continue to modify my dts in U-Boot so I can test things without me having to re-program the world. /shrug > As an extreme example, consider paravirtualization, where only a > small subset of DRAM and peripherals may be made available to any one > OS partition. Or AMP - though not likely that that is a problem for the D1.. > Fundamentally, I reserve the right to make arbitrary changes to the > DTB in the SBI implementation, and thus I cannot condone using the > DTBs generated from the Linux source tree for any purpose other than > validation. Fundamentally, I reserve the right to complain that the upstream dts cannot be entirely validated as it does not work out-of-the-box ;) Either way, I am only going to complain so much about something that triggers my OCD about keeping things the same, you have a Tested-by: Conor Dooley <conor.dooley@microchip.com> already and once the other issues are cleaned up an R-b too. Not trying make an issue out of this, just expressing my dislike for the inconsistency between the D1 stuff and vendors - partly in the hopes that the "higher powers" get involved. I can't imagine that this is the last time something like this comes up. Thanks, Conor.
Am Freitag, 9. September 2022, 09:18:40 CEST schrieb Conor.Dooley@microchip.com: > On 09/09/2022 05:37, Samuel Holland wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you > > know the content is safe > > > > Hi Conor, > > > > On 8/19/22 5:10 PM, Conor.Dooley@microchip.com wrote: > >> Finally got around to giving this a go with the fix for loading > >> modules which is mostly what was blocking me before.. > >> > >> On 15/08/2022 06:08, Samuel Holland wrote: > >>> "D1 Nezha" is Allwinner's first-party development board for the > >>> D1 SoC. It was shipped with 512M, 1G, or 2G of DDR3. It supports > >>> onboard audio, > >> > >> I am really not keen on the way you have things, with the memory > >> nodes removed from the device tree. I know your preferred flow for > >> booting these things might be to pass the dtb up from U-Boot, but I > >> think the devicetree in the kernel should be usable in a standalone > >> manner, even if that is the barest-minimum memory config. > > > > That is simply not possible to guarantee. As an obvious example, > > consider the MangoPi MQ-Pro board with socketed DRAM: > > Yeah, I knew in my heart-of-hearts that this probably was a non > runner. > > > > > https://twitter.com/mangopi_sbc/status/1516225559214583808 > > > > But focusing on the /memory node misses the bigger picture. The DTB > > is passed through _all_ of the firmware stages, and gets patched by > > every one of them: > > > > - SPL/boot0 adds the /memory node with the detected DRAM size. If the > > in-tree DTS has a "minimum memory config" (which for a board with > > socketed DRAM means the smallest possible die), I guarantee people > > will use it and complain about missing DRAM. > > True, but they are also complaining about missing DRAM as is ;) > No possibility of winning here unfortunately. > > > - The SBI implementation reserves memory for itself and any possible > > secure partitions. Right now, booting happens to work without the > > reserved-memory node because the SBI implementation is loaded at the > > beginning of RAM, and Linux ignores RAM below the kernel load > > address. > > Surely this sort of thing is a common problem though, it's not like > any of us are doing something unique here are we? At least if there > was a arch wide policy about the validity of the upstream DTS in the > face of the SBI etc inflicting changes there'd be something to point > to. I am just looking at this from a "everyone else has a usable dts > in the kernel, but the D1 boards wont have" point of view. Not sure if this would fly, but what about having an sbi call for "modify this dtb for me as well"? I'll just assume that spl/boot0 + main uboot come in some sort of package so moving the memory node over should be in uboot's scope, but for the sbi part just have a call pointing to the new dtb in memory and have it modify it in the same way as the original one? Heiko > > However, memory-constrained devices (e.g. D1s) will need to get those > > 2 MiB back by loading the kernel at the start of DRAM and SBI at the > > end of DRAM. Then the reserved-memory node becomes quite important. > > > > It also adds nodes for CPU idle states, since the available states > > and their latencies depend on the SBI implementation. > > > > It also reserves devices used by it or by a secure partition. And it > > is responsible for extracting data (e.g. MAC addresses) from "secure" > > eFuses which the OS may not have access to. > > > > - U-Boot adds other information, like boot arguments, the address of > > the initramfs and framebuffer, etc. These are less of a concern > > because of course U-Boot can patch these in to a DTB loaded from > > disk, but they are relevant if you want to load a DTB from a later > > bootloader like GRUB. > > > > If you load a DTB from disk, you lose all of the changes made by the > > earlier firmware stages. On ARM, U-Boot tries to work around this by > > copying a few specific bits of information from the firmware DTB to > > the DTB loaded from disk. But this misses the point that the SBI > > implementation can modify *any* part of the DTB. (So in practice > > U-Boot on ARM already loses CPU idle states and reserved memory nodes > > that were added by the PSCI implementation.) > > All of these things are valid, but they are reasons why your flow in > your bootloaders etc are the way they are more than a reason why the > upstream dts will not work for someone who is not interested in that > flow. At the end of the day, I only care so much about this as it is > not me that has to deal with any confusion from either approach. I'll > continue to modify my dts in U-Boot so I can test things without me > having to re-program the world. /shrug > > > As an extreme example, consider paravirtualization, where only a > > small subset of DRAM and peripherals may be made available to any one > > OS partition. > > Or AMP - though not likely that that is a problem for the D1.. > > > Fundamentally, I reserve the right to make arbitrary changes to the > > DTB in the SBI implementation, and thus I cannot condone using the > > DTBs generated from the Linux source tree for any purpose other than > > validation. > > Fundamentally, I reserve the right to complain that the upstream dts > cannot be entirely validated as it does not work out-of-the-box ;) > > Either way, I am only going to complain so much about something that > triggers my OCD about keeping things the same, you have a > Tested-by: Conor Dooley <conor.dooley@microchip.com> > already and once the other issues are cleaned up an R-b too. Not trying > make an issue out of this, just expressing my dislike for the > inconsistency between the D1 stuff and vendors - partly in the hopes > that the "higher powers" get involved. I can't imagine that this is > the last time something like this comes up. > > Thanks, > Conor. > > > > > >
On 9 Sept 2022, at 09:11, Heiko Stübner <heiko@sntech.de> wrote: > > Am Freitag, 9. September 2022, 09:18:40 CEST schrieb Conor.Dooley@microchip.com: >> On 09/09/2022 05:37, Samuel Holland wrote: >>> EXTERNAL EMAIL: Do not click links or open attachments unless you >>> know the content is safe >>> >>> Hi Conor, >>> >>> On 8/19/22 5:10 PM, Conor.Dooley@microchip.com wrote: >>>> Finally got around to giving this a go with the fix for loading >>>> modules which is mostly what was blocking me before.. >>>> >>>> On 15/08/2022 06:08, Samuel Holland wrote: >>>>> "D1 Nezha" is Allwinner's first-party development board for the >>>>> D1 SoC. It was shipped with 512M, 1G, or 2G of DDR3. It supports >>>>> onboard audio, >>>> >>>> I am really not keen on the way you have things, with the memory >>>> nodes removed from the device tree. I know your preferred flow for >>>> booting these things might be to pass the dtb up from U-Boot, but I >>>> think the devicetree in the kernel should be usable in a standalone >>>> manner, even if that is the barest-minimum memory config. >>> >>> That is simply not possible to guarantee. As an obvious example, >>> consider the MangoPi MQ-Pro board with socketed DRAM: >> >> Yeah, I knew in my heart-of-hearts that this probably was a non >> runner. >> >>> >>> https://twitter.com/mangopi_sbc/status/1516225559214583808 >>> >>> But focusing on the /memory node misses the bigger picture. The DTB >>> is passed through _all_ of the firmware stages, and gets patched by >>> every one of them: >>> >>> - SPL/boot0 adds the /memory node with the detected DRAM size. If the >>> in-tree DTS has a "minimum memory config" (which for a board with >>> socketed DRAM means the smallest possible die), I guarantee people >>> will use it and complain about missing DRAM. >> >> True, but they are also complaining about missing DRAM as is ;) >> No possibility of winning here unfortunately. >> >>> - The SBI implementation reserves memory for itself and any possible >>> secure partitions. Right now, booting happens to work without the >>> reserved-memory node because the SBI implementation is loaded at the >>> beginning of RAM, and Linux ignores RAM below the kernel load >>> address. >> >> Surely this sort of thing is a common problem though, it's not like >> any of us are doing something unique here are we? At least if there >> was a arch wide policy about the validity of the upstream DTS in the >> face of the SBI etc inflicting changes there'd be something to point >> to. I am just looking at this from a "everyone else has a usable dts >> in the kernel, but the D1 boards wont have" point of view. > > Not sure if this would fly, but what about having an sbi call for > "modify this dtb for me as well"? > > I'll just assume that spl/boot0 + main uboot come in some sort > of package so moving the memory node over should be in uboot's > scope, but for the sbi part just have a call pointing to the > new dtb in memory and have it modify it in the same way as the > original one? There’s an EFI protocol for it. Jess > Heiko > > > >>> However, memory-constrained devices (e.g. D1s) will need to get those >>> 2 MiB back by loading the kernel at the start of DRAM and SBI at the >>> end of DRAM. Then the reserved-memory node becomes quite important. >>> >>> It also adds nodes for CPU idle states, since the available states >>> and their latencies depend on the SBI implementation. >>> >>> It also reserves devices used by it or by a secure partition. And it >>> is responsible for extracting data (e.g. MAC addresses) from "secure" >>> eFuses which the OS may not have access to. >>> >>> - U-Boot adds other information, like boot arguments, the address of >>> the initramfs and framebuffer, etc. These are less of a concern >>> because of course U-Boot can patch these in to a DTB loaded from >>> disk, but they are relevant if you want to load a DTB from a later >>> bootloader like GRUB. >>> >>> If you load a DTB from disk, you lose all of the changes made by the >>> earlier firmware stages. On ARM, U-Boot tries to work around this by >>> copying a few specific bits of information from the firmware DTB to >>> the DTB loaded from disk. But this misses the point that the SBI >>> implementation can modify *any* part of the DTB. (So in practice >>> U-Boot on ARM already loses CPU idle states and reserved memory nodes >>> that were added by the PSCI implementation.) >> >> All of these things are valid, but they are reasons why your flow in >> your bootloaders etc are the way they are more than a reason why the >> upstream dts will not work for someone who is not interested in that >> flow. At the end of the day, I only care so much about this as it is >> not me that has to deal with any confusion from either approach. I'll >> continue to modify my dts in U-Boot so I can test things without me >> having to re-program the world. /shrug >> >>> As an extreme example, consider paravirtualization, where only a >>> small subset of DRAM and peripherals may be made available to any one >>> OS partition. >> >> Or AMP - though not likely that that is a problem for the D1.. >> >>> Fundamentally, I reserve the right to make arbitrary changes to the >>> DTB in the SBI implementation, and thus I cannot condone using the >>> DTBs generated from the Linux source tree for any purpose other than >>> validation. >> >> Fundamentally, I reserve the right to complain that the upstream dts >> cannot be entirely validated as it does not work out-of-the-box ;) >> >> Either way, I am only going to complain so much about something that >> triggers my OCD about keeping things the same, you have a >> Tested-by: Conor Dooley <conor.dooley@microchip.com> >> already and once the other issues are cleaned up an R-b too. Not trying >> make an issue out of this, just expressing my dislike for the >> inconsistency between the D1 stuff and vendors - partly in the hopes >> that the "higher powers" get involved. I can't imagine that this is >> the last time something like this comes up. >> >> Thanks, >> Conor. >> >> >> >> >> >> > > > > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile index f66554cd5c45..b0a15e8c8d82 100644 --- a/arch/riscv/boot/dts/allwinner/Makefile +++ b/arch/riscv/boot/dts/allwinner/Makefile @@ -1 +1,2 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi new file mode 100644 index 000000000000..143a3e710c3c --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> + +/ { + reg_vcc: vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_vcc_3v3: vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_vcc>; + }; +}; + +&lradc { + vref-supply = <®_aldo>; +}; + +&pio { + vcc-pb-supply = <®_vcc_3v3>; + vcc-pc-supply = <®_vcc_3v3>; + vcc-pd-supply = <®_vcc_3v3>; + vcc-pe-supply = <®_vcc_3v3>; + vcc-pf-supply = <®_vcc_3v3>; + vcc-pg-supply = <®_vcc_3v3>; +}; + +®_aldo { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vdd33-supply = <®_vcc_3v3>; +}; + +®_hpldo { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + hpldoin-supply = <®_vcc_3v3>; +}; + +®_ldoa { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + ldo-in-supply = <®_vcc_3v3>; +}; diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts new file mode 100644 index 000000000000..df865ee15fcf --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +#include "sun20i-d1.dtsi" +#include "sun20i-d1-common-regulators.dtsi" + +/ { + model = "Allwinner D1 Nezha"; + compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1"; + + aliases { + ethernet0 = &emac; + ethernet1 = &xr829; + mmc0 = &mmc0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_usbvbus: usbvbus { + compatible = "regulator-fixed"; + regulator-name = "usbvbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */ + enable-active-high; + vin-supply = <®_vcc>; + }; + + /* + * This regulator is PWM-controlled, but the PWM controller is not + * yet supported, so fix the regulator to its default voltage. + */ + reg_vdd_cpu: vdd-cpu { + compatible = "regulator-fixed"; + regulator-name = "vdd-cpu"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <®_vcc>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */ + }; +}; + +&cpu0 { + cpu-supply = <®_vdd_cpu>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + pinctrl-0 = <&rgmii_pe_pins>; + pinctrl-names = "default"; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii-id"; + phy-supply = <®_vcc_3v3>; + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pb0_pins>; + pinctrl-names = "default"; + status = "okay"; + + pcf8574a: gpio@38 { + compatible = "nxp,pcf8574a"; + reg = <0x38>; + interrupt-parent = <&pio>; + interrupts = <1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */ + interrupt-controller; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; +}; + +&lradc { + status = "okay"; + + button-160 { + label = "OK"; + linux,code = <KEY_OK>; + channel = <0>; + voltage = <160000>; + }; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mmc0 { + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + disable-wp; + vmmc-supply = <®_vcc_3v3>; + vqmmc-supply = <®_vcc_3v3>; + pinctrl-0 = <&mmc0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + vmmc-supply = <®_vcc_3v3>; + vqmmc-supply = <®_vcc_3v3>; + pinctrl-0 = <&mmc1_pins>; + pinctrl-names = "default"; + status = "okay"; + + xr829: wifi@1 { + reg = <1>; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb8_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + uart-has-rtscts; + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* XR829 bluetooth is connected here */ +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */ + usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ + usb0_vbus-supply = <®_usbvbus>; + usb1_vbus-supply = <®_vcc>; + status = "okay"; +};
"D1 Nezha" is Allwinner's first-party development board for the D1 SoC. It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard audio, HDMI, gigabit Ethernet, WiFi and Bluetooth, USB 2.0 host and OTG ports, plus low-speed I/O from the SoC and a GPIO expander chip. Most other D1 boards copied the Nezha's power tree, with the 1.8V rail powered by the SoCs internal LDOA, analog domains powered by ALDO, and the rest of the board powered by always-on fixed regulators. Some (but not all) boards also copied the PWM CPU regulator. To avoid duplication, factor out the out the regulator references that are common across all known boards. Signed-off-by: Samuel Holland <samuel@sholland.org> --- arch/riscv/boot/dts/allwinner/Makefile | 1 + .../sun20i-d1-common-regulators.dtsi | 51 ++++++ .../boot/dts/allwinner/sun20i-d1-nezha.dts | 171 ++++++++++++++++++ 3 files changed, 223 insertions(+) create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts