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([109.76.58.63]) by smtp.gmail.com with ESMTPSA id i15-20020a05600c354f00b003a5dfd7e9eesm3029371wmq.44.2022.08.17.13.12.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Aug 2022 13:12:47 -0700 (PDT) From: Conor Dooley To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: Daniel Lezcano , Anup Patel , Conor Dooley , Guo Ren , Sagar Kadam , Jessica Clarke , Andrew Jones , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, qemu-riscv@nongnu.org Subject: [NOT FOR INCLUSION v3 4/4] dt-bindings: riscv: isa string bonus content Date: Wed, 17 Aug 2022 21:12:13 +0100 Message-Id: <20220817201212.990712-5-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220817201212.990712-1-mail@conchuod.ie> References: <20220817201212.990712-1-mail@conchuod.ie> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220817_131253_006756_E9FF7EEC X-CRM114-Status: GOOD ( 10.40 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley **NOT FOR INCLUSION** I figured, sure why not add the strings for version number validation, just in case we need them in the future. The commented out string is considered by dt-schema to be "not a regex", but regex101 thinks it is... Maybe dt-schema does not support named match groups, but they are the only way that I could trivially find to make this somewhat manageable. Either way, it is permissive so it allows combinations of "M", "MpM" & no number. Not-signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index c0e0bc5dce04..38a824453012 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -80,7 +80,11 @@ properties: insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing. $ref: "/schemas/types.yaml#/definitions/string" - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:(?:_[zsh][imafdqcbvksh]|_x)(?:[a-z])+)*$ + oneOf: + - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:(?:_[zsh][imafdqcbvksh]|_x)(?:[a-z])+)*$ + - pattern: ^rv(?:64|32)(?:i\d+)(?:m\d+)(?:a\d+)(?:f\d+)?(?:d\d+)?(?:q\d+)?(?:c\d+)?(?:b\d+)?(?:v\d+)?(?:k\d+)?(?:h\d+)?(?:(?:_[zsh][imafdqcbvksh]|_x)(?:[a-z])+\d+)*$ + - pattern: ^rv(?:64|32)(?:i\d+p\d+)(?:m\d+p\d+)(?:a\d+p\d+)(?:f\d+p\d+)?(?:d\d+p\d+)?(?:q\d+p\d+)?(?:c\d+p\d+)?(?:b\d+p\d+)?(?:v\d+p\d+)?(?:k\d+p\d+)?(?:h\d+p\d+)?(?:(?:_[zsh][imafdqcbvksh]|_x)(?:[a-z])+(?:\d+p\d+))*$ +# - pattern: ^rv(?:64|32)(?:i(?(?:\d+|\d+p\d+)?)?)(?:m(?:\k)?)(?:a(?:\k)?)(?:f(?:\k)?)?(?:d(?:\k)?)?(?:q(?:\k)?)?(?:c(?:\k)?)?(?:b(?:\k)?)?(?:v(?:\k)?)?(?:k(?:\k)?)?(?:h(?:\k)?)?(?:(?:_[zsh][imafdqcbvksh]|_x)(?:[a-z])*(?:\d+|\d+p\d+)?)+$ # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false