| Message ID | 20220819122259.183600-6-conor.dooley@microchip.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add PolarFire SoC Fabric Clock Conditioning Circuitry Support | expand |
On 19/08/2022 15:22, Conor Dooley wrote: > Add a new compatible for the icicle kit reference design's 22.09 > release, which made some changes to the memory map - including adding > the ability to read the CCCs via the system controller bus. Technically > that was always possible, but the specific CC chosen could vary per > run of the synthesis tool. Hopefully this is the last reference design > version impacting the memory map. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 1aa7336a9672..928ce4d4e087 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -21,6 +21,7 @@ properties: - enum: - microchip,mpfs-icicle-kit - microchip,mpfs-icicle-reference-rtlv2203 + - microchip,mpfs-icicle-reference-rtlv2209 - sundance,polarberry - const: microchip,mpfs
Add a new compatible for the icicle kit reference design's 22.09 release, which made some changes to the memory map - including adding the ability to read the CCCs via the system controller bus. Technically that was always possible, but the specific CC chosen could vary per run of the synthesis tool. Hopefully this is the last reference design version impacting the memory map. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- Documentation/devicetree/bindings/riscv/microchip.yaml | 1 + 1 file changed, 1 insertion(+)