From patchwork Fri Aug 26 14:28:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12956100 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 570D2ECAAA3 for ; Fri, 26 Aug 2022 14:29:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=G4PiJV7C58qCVYLmRMSDcTeT/dsz/rIUdT3FVZI3G/U=; b=YyPF777dspRwAN FKGNE3MTmcCWS+gdT3E3uAN3Z9CJLd3PSQrgjUTIPFVg/0JnuFBZJwIJdM9GVStEa9y40xrfkdmPx SrgDkydcMpsYUvn0Zz//yo3AiCQwhOG5YEpXkjJ4M1s93O6BYKy9kWZhLVPYIaDg30s7agDDB6LJ6 rVRGU1jCsvnvXkHsDmm/eIO3D0XB+7kp38WoR1A3DFgLvcKyK4nots1k0ZVnpUsfq09XVrBquOfo9 1+3JiyWLNN1XsrGXDUJzsfBIDv9JPlviLz4XFV3PuDqWnceEMWaaZ8KXJFETqMRcsRISeDbSS8e/p BLLVd2CUKPgmMOFHY2lg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oRaKX-006CqZ-B3; Fri, 26 Aug 2022 14:29:05 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oRaKS-006CTX-4s for linux-riscv@lists.infradead.org; Fri, 26 Aug 2022 14:29:01 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661524139; x=1693060139; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fKL2pKdfe49aKzGqeWYbXuxKM2r4HTWOwpLHntUQotA=; b=tl1PP4p9SlhEYjjlNXAdReCpMzCl1KyImUH+vzah2V2fwDTLBFZ39AyV NwrRzrCneOZ0wCQq3uXK0wZYaDbXecvxbfXS7bzpga+4vxfrgMXAPcCcT biwBIGy7x7QJvNIiPQFYJ5UU0CcQAEKyFn5iUUISulMxaDVrRAnDBzt0o nIRbFip1MoyQquizmFTJpREEWqoSgYILYHfpdLKfWdTlnoTCHRR/B7hx4 AiFEM0EVbtYZcFIcWOycytShpN0YJqrD6IvBPujKtEzwRzPbmFEROQB+C Boy4vMJX6lLyVconaHmDjuxNAqttOn3iSSUP6NDhw31YmX7YQNdMpPkH6 Q==; X-IronPort-AV: E=Sophos;i="5.93,265,1654585200"; d="scan'208";a="110917618" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Aug 2022 07:28:59 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 26 Aug 2022 07:28:59 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 26 Aug 2022 07:28:56 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , , , Subject: [PATCH 6/9] riscv: dts: microchip: icicle: update pci address properties Date: Fri, 26 Aug 2022 15:28:04 +0100 Message-ID: <20220826142806.3658434-7-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220826142806.3658434-1-conor.dooley@microchip.com> References: <20220826142806.3658434-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220826_072900_279779_E11B34AF X-CRM114-Status: UNSURE ( 9.46 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org For the v2022.09 reference design the PCI root port's data region has been moved to FIC1 from FIC0. This is a shorter path, allowing for higher clock rates and improved through-put. As a result, the address at which the PCIe's data region appears to the core complex has changed. The config region's address is unchanged. As FIC0 is no longer used, its clock can be removed too. Signed-off-by: Conor Dooley --- .../boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index a21440c8ee03..32d51c4a5b0c 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -2,6 +2,7 @@ /* Copyright (c) 2020-2021 Microchip Technology Inc */ / { + compatible = "microchip,mpfs-icicle-reference-rtlv2209", "microchip,mpfs-icicle-kit", "microchip,mpfs"; @@ -38,13 +39,13 @@ fabric_clk1: fabric-clk1 { clock-frequency = <125000000>; }; - pcie: pcie@2000000000 { + pcie: pcie@3000000000 { compatible = "microchip,pcie-host-1.0"; #address-cells = <0x3>; #interrupt-cells = <0x1>; #size-cells = <0x2>; device_type = "pci"; - reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; reg-names = "cfg", "apb"; bus-range = <0x0 0x7f>; interrupt-parent = <&plic>; @@ -54,9 +55,9 @@ pcie: pcie@2000000000 { <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; interrupt-map-mask = <0 0 0 7>; - clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; - clock-names = "fic0", "fic1", "fic3"; - ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + clocks = <&fabric_clk1>, <&fabric_clk3>; + clock-names = "fic1", "fic3"; + ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>; dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; msi-parent = <&pcie>; msi-controller;