From patchwork Fri Sep 9 12:31:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12971709 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C16BFC6FA8E for ; Fri, 9 Sep 2022 12:32:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=wWxvAujqaPY0V25+7+dpInaxC1mlQwVZIijNdjYfgfU=; b=FN3XW+ps7Ulpkf CffIaKtGroyNVwt4gEpFmiRPJRPo+FFjMjLxu/C+W+cNl3BYkc51BqdYjw7VI3Lh/TVynR3lPIwFZ YclWrEUzOaTOtDWtYPcqECIfPCxj5MHmcnyFogbjBOrQzeb3pqfDAMdcKpXrpJ4QMTFTJj95XO4Ih cmqRPV9qWNzwDWgyQKFQsY7vVQWEtD+lX1onx83N+i6WOeHYuVYeYRRSataAoFc/sRHaPbcwLDSCd 2fwsaYJXyno6eqd9aa638wB98TyfNXMJqo8U7SbrcDk8Wtl4uK7cHE7aiqEOZn63BKhSRObePD05y nozUk+h5ba/Njwgc1u/A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oWdB6-00G2Bz-Ed; Fri, 09 Sep 2022 12:32:12 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oWdB0-00G25X-Jk for linux-riscv@lists.infradead.org; Fri, 09 Sep 2022 12:32:08 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662726726; x=1694262726; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fdjX5tbqzbcZLdj3QtoTUweKd5AlbElmyy/Hw5S6d5w=; b=ekz51cJSGBSOO4uI2lm0Na190SkPo5lvANnKf/zluV7rumXH6KzBS+D9 Zx2Lwhp10P+X9SQm5+J7YZz/DuxFkqgPve4G6rUnxd8N/2TxJPkWGQOzf zCSuT3vO9OiuePEKHB8siHeUehRU86EJ1xVX2zN8IsffxkW5ijLV7d7Yw PiveCpfj4/UCqxlD+7zfz8wkds89lFhM/Q3wArkGSZELlR2Pmn6n2Uza2 nZq8XXTuq3dIZMpFWOclPJ3yiaDd3ap1bZwdiVH8f/et8cofaxiwY5CTm dScvRWoDha4Bgg9vwWZyUy6v2zu3TS0/oF590AHUHym8T8CrLegVSigod w==; X-IronPort-AV: E=Sophos;i="5.93,303,1654585200"; d="scan'208";a="176399164" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Sep 2022 05:31:56 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 9 Sep 2022 05:31:54 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 9 Sep 2022 05:31:52 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Daire McNamara CC: Paul Walmsley , Albert Ou , Claudiu Beznea , , , , , "Rob Herring" Subject: [PATCH v5 03/14] dt-bindings: clk: microchip: mpfs: add reset controller support Date: Fri, 9 Sep 2022 13:31:12 +0100 Message-ID: <20220909123123.2699583-4-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220909123123.2699583-1-conor.dooley@microchip.com> References: <20220909123123.2699583-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220909_053206_751602_4474006B X-CRM114-Status: GOOD ( 10.91 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The "peripheral" devices on PolarFire SoC can be put into reset, so update the device tree binding to reflect the presence of a reset controller. Reviewed-by: Rob Herring Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley --- .../bindings/clock/microchip,mpfs.yaml | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml index 016a4f378b9b..1d0b6a4fda42 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml @@ -40,8 +40,21 @@ properties: const: 1 description: | The clock consumer should specify the desired clock by having the clock - ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h - for the full list of PolarFire clock IDs. + ID in its "clocks" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of + PolarFire clock IDs. + + resets: + maxItems: 1 + + '#reset-cells': + description: + The AHB/AXI peripherals on the PolarFire SoC have reset support, so from + CLK_ENVM to CLK_CFM. The reset consumer should specify the desired + peripheral via the clock ID in its "resets" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of + PolarFire clock IDs. + const: 1 required: - compatible