From patchwork Fri Sep 9 12:31:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12971712 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2A0D6ECAAA1 for ; Fri, 9 Sep 2022 12:32:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=s+oqRXOMk94B2gqFrJmXAs2gOf4wCnTce4QS9OORP9g=; b=h4ELFwpAEhcLIU vgy8uE1AcbxapFgvfa6ro15ddfQsP0N+/KxAL9IxTsUQJO6x2ZK7+jsomSqAoaiN1Q4O3NKumZKDN K5sBOKWsapUQdwCuh7JDljnh7HpwomrIaiT/L3V8he2zDZX2tO8OTgs2r7l/GlZzRFuHMLvTm+b+P Rj0GqfvDcW28pPm/2zm0Jkmv2UeoB/wd7gRjGjRiDLFAr5HhAIqEBgqoUoca2gNi/lmtKTYuGnd1Y X/lInvlsUKfHGzHPirQKEho2L5beHhwlJheEMQwBd068Ols1Jjmmdh9sKgD561X3IvSFHyYJH3JHB SZTetbEc2qaNCCkpZM+g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oWdBC-00G2HX-Tl; Fri, 09 Sep 2022 12:32:18 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oWdB9-00G2EC-BA for linux-riscv@lists.infradead.org; Fri, 09 Sep 2022 12:32:16 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662726735; x=1694262735; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+IIVc307auJRgXB9wfntqv2uBJ0XjYajuLGf8lU3Pmg=; b=YbbXFgT5D7DOebxO5L9YLAj/PLQiywybbd3QMTrHcET/UQyUNJBrU8MM 06+D6YGQAQkt3BHJiCk9EZdLeP7DqPx240r67unz+1Eiy5A5PdchaXuRS IGFSzZNGpiQRy1FSm8hVbw0rBvw481tDOfQOtZwXhNjlUik+YAchG17mM 1rTk/tZnIddkgOS+0TcFaUEjxeW6Jbj1ywgJam1lTe2Sc1RCW1DjWwBN4 nnYAKSlQAzGafiHERt6dfSkRHap49IK79H++2uLKC6TOzeipfd6YIzYuP nihODqAjMyCUR/N4nLf01IZ3bllGMV2eB2yOKyD4UNkMMM/lkSELRNaKb g==; X-IronPort-AV: E=Sophos;i="5.93,303,1654585200"; d="scan'208";a="112926442" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Sep 2022 05:32:10 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 9 Sep 2022 05:32:09 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 9 Sep 2022 05:32:06 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Daire McNamara CC: Paul Walmsley , Albert Ou , Claudiu Beznea , , , , Subject: [PATCH v5 08/14] clk: microchip: mpfs: add MSS pll's set & round rate Date: Fri, 9 Sep 2022 13:31:17 +0100 Message-ID: <20220909123123.2699583-9-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220909123123.2699583-1-conor.dooley@microchip.com> References: <20220909123123.2699583-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220909_053215_501975_911C4CCC X-CRM114-Status: GOOD ( 10.71 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The MSS pll is not a fixed frequency clock, so add set() & round_rate() support. Control is limited to a 7 bit output divider as other devices on the FPGA occupy the other three outputs of the PLL & prevent changing the multiplier. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley Reviewed-by: Claudiu Beznea --- drivers/clk/microchip/clk-mpfs.c | 54 ++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index 610c81ecc526..f40d22293539 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -129,8 +129,62 @@ static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned lon return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv); } +static long mpfs_clk_msspll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) +{ + struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); + void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; + void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; + u32 mult, ref_div; + unsigned long rate_before_ctrl; + + mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; + mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); + ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; + ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); + + rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; + + return divider_round_rate(hw, rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, + msspll_hw->flags); +} + +static int mpfs_clk_msspll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) +{ + struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); + void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; + void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; + void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; + u32 mult, ref_div, postdiv; + int divider_setting; + unsigned long rate_before_ctrl, flags; + + mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; + mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); + ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; + ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); + + rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; + divider_setting = divider_get_val(rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, + msspll_hw->flags); + + if (divider_setting < 0) + return divider_setting; + + spin_lock_irqsave(&mpfs_clk_lock, flags); + + postdiv = readl_relaxed(postdiv_addr); + postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT); + writel_relaxed(postdiv, postdiv_addr); + + spin_unlock_irqrestore(&mpfs_clk_lock, flags); + + return 0; +} + static const struct clk_ops mpfs_clk_msspll_ops = { .recalc_rate = mpfs_clk_msspll_recalc_rate, + .round_rate = mpfs_clk_msspll_round_rate, + .set_rate = mpfs_clk_msspll_set_rate, }; #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \