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[99.152.116.91]) by smtp.gmail.com with ESMTPSA id bf10-20020a170902b90a00b0017849a2b56asm89488plb.46.2022.09.20.09.00.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Sep 2022 09:00:48 -0700 (PDT) From: Olof Johansson To: Greg Kroah-Hartman Cc: Jiri Slaby , linux-serial@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Olof Johansson , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Emil Renner Berthing , Palmer Dabbelt , Paul Walmsley Subject: [PATCH v2] serial: sifive: enable clocks for UART when probed Date: Tue, 20 Sep 2022 09:00:18 -0700 Message-Id: <20220920160017.7315-1-olof@lixom.net> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220920_090055_555486_0C5AAA50 X-CRM114-Status: GOOD ( 13.92 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org When the PWM driver was changed to disable clocks if no PWMs are enabled, it ended up also disabling the shared parent with the UART, since the UART doesn't do any clock enablement on its own. To avoid these surprises, switch to clk_get_enabled(). Fixes: ace41d7564e655 ("pwm: sifive: Ensure the clk is enabled exactly once per running PWM") Cc: Uwe Kleine-König Cc: Emil Renner Berthing Cc: Palmer Dabbelt Cc: Paul Walmsley Signed-off-by: Olof Johansson Reviewed-by: Uwe Kleine-König Acked-by: Palmer Dabbelt Reviewed-by: Palmer Dabbelt --- v2: Switch to devm_clk_enabled() per Uwe's suggestion. --- drivers/tty/serial/sifive.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/tty/serial/sifive.c b/drivers/tty/serial/sifive.c index 5c3a07546a58..4b1d4fe8458e 100644 --- a/drivers/tty/serial/sifive.c +++ b/drivers/tty/serial/sifive.c @@ -945,7 +945,7 @@ static int sifive_serial_probe(struct platform_device *pdev) return PTR_ERR(base); } - clk = devm_clk_get(&pdev->dev, NULL); + clk = devm_clk_get_enabled(&pdev->dev, NULL); if (IS_ERR(clk)) { dev_err(&pdev->dev, "unable to find controller clock\n"); return PTR_ERR(clk);