diff mbox series

[RFC,07/27] riscv: replace SOC_STARFIVE with ARCH_STARFIVE

Message ID 20220923185605.1900083-8-conor@kernel.org (mailing list archive)
State RFC, archived
Headers show
Series RISC-V: Convert SOC_FOO symbols to ARCH_FOO | expand

Commit Message

Conor Dooley Sept. 23, 2022, 6:55 p.m. UTC 
From: Conor Dooley <conor.dooley@microchip.com>

As discussed at LPC, the SOC_ symbols are being converted to ARCH_
for the sake of consistency between "incumbent" vendors and those who
have a legacy from other archs.

Convert SOC_STARFIVE to ARCH_STARFIVE across arch/riscv

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/Kconfig.socs               | 2 +-
 arch/riscv/boot/dts/starfive/Makefile | 2 +-
 arch/riscv/configs/defconfig          | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

Comments

Heiko Stuebner Sept. 23, 2022, 7:09 p.m. UTC | #1 
Hi Conor,

Am Freitag, 23. September 2022, 20:55:46 CEST schrieb Conor Dooley:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> As discussed at LPC, the SOC_ symbols are being converted to ARCH_
> for the sake of consistency between "incumbent" vendors and those who
> have a legacy from other archs.
> 
> Convert SOC_STARFIVE to ARCH_STARFIVE across arch/riscv
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  arch/riscv/Kconfig.socs               | 2 +-
>  arch/riscv/boot/dts/starfive/Makefile | 2 +-
>  arch/riscv/configs/defconfig          | 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index c4c7add1516f..910697baf097 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -17,7 +17,7 @@ config SOC_SIFIVE
>  	help
>  	  This enables support for SiFive SoC platform hardware.
>  
> -config SOC_STARFIVE
> +config ARCH_STARFIVE

doesn't this create a bisection issue?
I.e. the clk-Makefile in the following patch will still do

	obj-$(CONFIG_SOC_STARFIVE)             += starfive/

at this point, so if a git bisect lands here, you stop building
the clock-driver (and maybe more).

I guess some intermediate solution might be helpful, like
introduce the ARCH_STARFIVE and make SOC_STARFIVE select it.
Then do the conversions and after that drop SOC_STARFIVE?


Heiko


>  	bool "StarFive SoCs"
>  	select PINCTRL
>  	select RESET_CONTROLLER
> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> index 039c143cba33..7b00a48580ca 100644
> --- a/arch/riscv/boot/dts/starfive/Makefile
> +++ b/arch/riscv/boot/dts/starfive/Makefile
> @@ -1,2 +1,2 @@
>  # SPDX-License-Identifier: GPL-2.0
> -dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
> +dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index dac14b95c73d..971986be875f 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -27,7 +27,7 @@ CONFIG_EXPERT=y
>  CONFIG_PROFILING=y
>  CONFIG_ARCH_MICROCHIP_POLARFIRE=y
>  CONFIG_SOC_SIFIVE=y
> -CONFIG_SOC_STARFIVE=y
> +CONFIG_ARCH_STARFIVE=y
>  CONFIG_SOC_VIRT=y
>  CONFIG_SMP=y
>  CONFIG_HOTPLUG_CPU=y
>
Conor Dooley Sept. 23, 2022, 7:14 p.m. UTC | #2 
On Fri, Sep 23, 2022 at 09:09:03PM +0200, Heiko Stuebner wrote:
> Hi Conor,
> 
> Am Freitag, 23. September 2022, 20:55:46 CEST schrieb Conor Dooley:
> > From: Conor Dooley <conor.dooley@microchip.com>
> > 
> > As discussed at LPC, the SOC_ symbols are being converted to ARCH_
> > for the sake of consistency between "incumbent" vendors and those who
> > have a legacy from other archs.
> > 
> > Convert SOC_STARFIVE to ARCH_STARFIVE across arch/riscv
> > 
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> >  arch/riscv/Kconfig.socs               | 2 +-
> >  arch/riscv/boot/dts/starfive/Makefile | 2 +-
> >  arch/riscv/configs/defconfig          | 2 +-
> >  3 files changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > index c4c7add1516f..910697baf097 100644
> > --- a/arch/riscv/Kconfig.socs
> > +++ b/arch/riscv/Kconfig.socs
> > @@ -17,7 +17,7 @@ config SOC_SIFIVE
> >  	help
> >  	  This enables support for SiFive SoC platform hardware.
> >  
> > -config SOC_STARFIVE
> > +config ARCH_STARFIVE
> 
> doesn't this create a bisection issue?

Yeah, I thought of that midway through and then promptly forgot about
it... I'll sort it out for v1.

Thanks.

> I.e. the clk-Makefile in the following patch will still do
> 
> 	obj-$(CONFIG_SOC_STARFIVE)             += starfive/
> 
> at this point, so if a git bisect lands here, you stop building
> the clock-driver (and maybe more).
> 
> I guess some intermediate solution might be helpful, like
> introduce the ARCH_STARFIVE and make SOC_STARFIVE select it.
> Then do the conversions and after that drop SOC_STARFIVE?
> 
> 
> Heiko
> 
> 
> >  	bool "StarFive SoCs"
> >  	select PINCTRL
> >  	select RESET_CONTROLLER
> > diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> > index 039c143cba33..7b00a48580ca 100644
> > --- a/arch/riscv/boot/dts/starfive/Makefile
> > +++ b/arch/riscv/boot/dts/starfive/Makefile
> > @@ -1,2 +1,2 @@
> >  # SPDX-License-Identifier: GPL-2.0
> > -dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
> > +dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
> > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> > index dac14b95c73d..971986be875f 100644
> > --- a/arch/riscv/configs/defconfig
> > +++ b/arch/riscv/configs/defconfig
> > @@ -27,7 +27,7 @@ CONFIG_EXPERT=y
> >  CONFIG_PROFILING=y
> >  CONFIG_ARCH_MICROCHIP_POLARFIRE=y
> >  CONFIG_SOC_SIFIVE=y
> > -CONFIG_SOC_STARFIVE=y
> > +CONFIG_ARCH_STARFIVE=y
> >  CONFIG_SOC_VIRT=y
> >  CONFIG_SMP=y
> >  CONFIG_HOTPLUG_CPU=y
> > 
> 
> 
> 
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Heiko Stuebner Sept. 23, 2022, 7:20 p.m. UTC | #3 
Am Freitag, 23. September 2022, 21:14:58 CEST schrieb Conor Dooley:
> On Fri, Sep 23, 2022 at 09:09:03PM +0200, Heiko Stuebner wrote:
> > Hi Conor,
> > 
> > Am Freitag, 23. September 2022, 20:55:46 CEST schrieb Conor Dooley:
> > > From: Conor Dooley <conor.dooley@microchip.com>
> > > 
> > > As discussed at LPC, the SOC_ symbols are being converted to ARCH_
> > > for the sake of consistency between "incumbent" vendors and those who
> > > have a legacy from other archs.
> > > 
> > > Convert SOC_STARFIVE to ARCH_STARFIVE across arch/riscv
> > > 
> > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > > ---
> > >  arch/riscv/Kconfig.socs               | 2 +-
> > >  arch/riscv/boot/dts/starfive/Makefile | 2 +-
> > >  arch/riscv/configs/defconfig          | 2 +-
> > >  3 files changed, 3 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > > index c4c7add1516f..910697baf097 100644
> > > --- a/arch/riscv/Kconfig.socs
> > > +++ b/arch/riscv/Kconfig.socs
> > > @@ -17,7 +17,7 @@ config SOC_SIFIVE
> > >  	help
> > >  	  This enables support for SiFive SoC platform hardware.
> > >  
> > > -config SOC_STARFIVE
> > > +config ARCH_STARFIVE
> > 
> > doesn't this create a bisection issue?
> 
> Yeah, I thought of that midway through and then promptly forgot about
> it... I'll sort it out for v1.

It's of course the same for sifive and probably more.

ARCH_MICROCHIP was pre-existing in your series, so that transistion
goes way smoother - though I haven't been able to find where that
symbol actually got added :-) .

I.e. in Palmers next branchs the symbol is still SOC_MICROCHIP_POLARFIRE

Heiko


> > I.e. the clk-Makefile in the following patch will still do
> > 
> > 	obj-$(CONFIG_SOC_STARFIVE)             += starfive/
> > 
> > at this point, so if a git bisect lands here, you stop building
> > the clock-driver (and maybe more).
> > 
> > I guess some intermediate solution might be helpful, like
> > introduce the ARCH_STARFIVE and make SOC_STARFIVE select it.
> > Then do the conversions and after that drop SOC_STARFIVE?
> > 
> > 
> > Heiko
> > 
> > 
> > >  	bool "StarFive SoCs"
> > >  	select PINCTRL
> > >  	select RESET_CONTROLLER
> > > diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> > > index 039c143cba33..7b00a48580ca 100644
> > > --- a/arch/riscv/boot/dts/starfive/Makefile
> > > +++ b/arch/riscv/boot/dts/starfive/Makefile
> > > @@ -1,2 +1,2 @@
> > >  # SPDX-License-Identifier: GPL-2.0
> > > -dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
> > > +dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
> > > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> > > index dac14b95c73d..971986be875f 100644
> > > --- a/arch/riscv/configs/defconfig
> > > +++ b/arch/riscv/configs/defconfig
> > > @@ -27,7 +27,7 @@ CONFIG_EXPERT=y
> > >  CONFIG_PROFILING=y
> > >  CONFIG_ARCH_MICROCHIP_POLARFIRE=y
> > >  CONFIG_SOC_SIFIVE=y
> > > -CONFIG_SOC_STARFIVE=y
> > > +CONFIG_ARCH_STARFIVE=y
> > >  CONFIG_SOC_VIRT=y
> > >  CONFIG_SMP=y
> > >  CONFIG_HOTPLUG_CPU=y
> > > 
> > 
> > 
> > 
> > 
> > 
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
>
Conor Dooley Sept. 23, 2022, 7:22 p.m. UTC | #4 
On 23/09/2022 20:20, Heiko Stuebner wrote:
> Am Freitag, 23. September 2022, 21:14:58 CEST schrieb Conor Dooley:
>> On Fri, Sep 23, 2022 at 09:09:03PM +0200, Heiko Stuebner wrote:
>>> Hi Conor,
>>>
>>> Am Freitag, 23. September 2022, 20:55:46 CEST schrieb Conor Dooley:
>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>
>>>> As discussed at LPC, the SOC_ symbols are being converted to ARCH_
>>>> for the sake of consistency between "incumbent" vendors and those who
>>>> have a legacy from other archs.
>>>>
>>>> Convert SOC_STARFIVE to ARCH_STARFIVE across arch/riscv
>>>>
>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>> ---
>>>>  arch/riscv/Kconfig.socs               | 2 +-
>>>>  arch/riscv/boot/dts/starfive/Makefile | 2 +-
>>>>  arch/riscv/configs/defconfig          | 2 +-
>>>>  3 files changed, 3 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
>>>> index c4c7add1516f..910697baf097 100644
>>>> --- a/arch/riscv/Kconfig.socs
>>>> +++ b/arch/riscv/Kconfig.socs
>>>> @@ -17,7 +17,7 @@ config SOC_SIFIVE
>>>>  	help
>>>>  	  This enables support for SiFive SoC platform hardware.
>>>>  
>>>> -config SOC_STARFIVE
>>>> +config ARCH_STARFIVE
>>>
>>> doesn't this create a bisection issue?
>>
>> Yeah, I thought of that midway through and then promptly forgot about
>> it... I'll sort it out for v1.
> 
> It's of course the same for sifive and probably more.
> 
> ARCH_MICROCHIP was pre-existing in your series, so that transistion
> goes way smoother - though I haven't been able to find where that
> symbol actually got added :-) .
> 
> I.e. in Palmers next branchs the symbol is still SOC_MICROCHIP_POLARFIRE

Ah for god's sake, I gave the wrong hash to format-patch lol.

I didn't check carefully to be honest as I wasn't too concerned about
the content and more about how I would break the series up!

I am glad I said RFC...
diff mbox series

Patch

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index c4c7add1516f..910697baf097 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -17,7 +17,7 @@  config SOC_SIFIVE
 	help
 	  This enables support for SiFive SoC platform hardware.
 
-config SOC_STARFIVE
+config ARCH_STARFIVE
 	bool "StarFive SoCs"
 	select PINCTRL
 	select RESET_CONTROLLER
diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index 039c143cba33..7b00a48580ca 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -1,2 +1,2 @@ 
 # SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
+dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index dac14b95c73d..971986be875f 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -27,7 +27,7 @@  CONFIG_EXPERT=y
 CONFIG_PROFILING=y
 CONFIG_ARCH_MICROCHIP_POLARFIRE=y
 CONFIG_SOC_SIFIVE=y
-CONFIG_SOC_STARFIVE=y
+CONFIG_ARCH_STARFIVE=y
 CONFIG_SOC_VIRT=y
 CONFIG_SMP=y
 CONFIG_HOTPLUG_CPU=y