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[31.30.173.61]) by smtp.gmail.com with ESMTPSA id e15-20020a50fb8f000000b00459f4974128sm6825179edq.50.2022.10.10.02.40.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 02:40:30 -0700 (PDT) From: Andrew Jones To: kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org Cc: anup@brainfault.org, atishp@atishpatra.org, conor.dooley@microchip.com, vernon2gm@gmail.com, kernel test robot Subject: [PATCH] RISC-V: KVM: Fix compilation without RISCV_ISA_ZICBOM Date: Mon, 10 Oct 2022 11:40:29 +0200 Message-Id: <20221010094029.1579672-1-ajones@ventanamicro.com> X-Mailer: git-send-email 2.37.3 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221010_024035_390374_853E5B16 X-CRM114-Status: UNSURE ( 8.71 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Fix undefined reference of riscv_cbom_block_size when compiling KVM without RISCV_ISA_ZICBOM. Note, RISCV_ISA_ZICBOM is a sufficient guard as it selects RISCV_DMA_NONCOHERENT, which is needed to compile dma-noncoherent.c (which is the file where riscv_cbom_block_size and its initializer live). Fixes: afd5dde9a186 ("RISC-V: KVM: Provide UAPI for Zicbom block size") Reported-by: kernel test robot Signed-off-by: Andrew Jones --- arch/riscv/kvm/vcpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index a032c4f0d600..e4453caba728 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -265,11 +265,13 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu, case KVM_REG_RISCV_CONFIG_REG(isa): reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK; break; +#ifdef CONFIG_RISCV_ISA_ZICBOM case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size): if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM)) return -EINVAL; reg_val = riscv_cbom_block_size; break; +#endif default: return -EINVAL; }