From patchwork Thu Nov 10 16:49:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 13039012 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 74855C4332F for ; Thu, 10 Nov 2022 16:50:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=1Euu4DQ6+h6tSBM02B87cj3WuDWl6BStp1qjoTDZLhY=; b=bY+NHoNGc65Xxq rGc/t/x4TIE4xFK3DoWUCY7GoL4fUKLL8vSA5WMJRLv0s0fa5OT1zQEVznyZ6f8XARF7jd74AfyeZ 5bhUsaaULMCvXairTdW0V/NgkJbhh6a/RTByDLykewPPmOKqNJxHQ/y/HQeXDTlyDVW2oVspZQjhE 2uhUk5kJpdN748to1GfMiLhgpQC4GPyy5FXeqM0epRdUhKe1zoif4lLABVjFHtu93SHqy5U+RsgmL St1VabL/vuTAAWJhCjF2Ci9klE2ipdEvZzM/Pv3J3U7AfcC/KKAP0uxJEPVFQ34EbtOAbi+kDSdUd FvdT8d0GhCYuEwhvUxcQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1otAkr-007KNw-79; Thu, 10 Nov 2022 16:50:17 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1otAko-007KIE-6k for linux-riscv@lists.infradead.org; Thu, 10 Nov 2022 16:50:15 +0000 Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1otAkk-0001xU-QO; Thu, 10 Nov 2022 17:50:10 +0100 From: Heiko Stuebner To: linux-riscv@lists.infradead.org, palmer@dabbelt.com Cc: christoph.muellner@vrull.eu, prabhakar.csengg@gmail.com, conor@kernel.org, philipp.tomsich@vrull.eu, ajones@ventanamicro.com, heiko@sntech.de, emil.renner.berthing@canonical.com, Heiko Stuebner Subject: [PATCH 3/7] RISC-V: add U-type imm parsing to parse_asm header Date: Thu, 10 Nov 2022 17:49:20 +0100 Message-Id: <20221110164924.529386-4-heiko@sntech.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221110164924.529386-1-heiko@sntech.de> References: <20221110164924.529386-1-heiko@sntech.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221110_085014_276505_EC5EE3FF X-CRM114-Status: GOOD ( 12.09 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Heiko Stuebner Similar to other existing types, allow extracting the immediate for a U-type instruction. U-type immediates are special in that regard, that the value in the instruction in bits [31:12] already represents the same bits of the immediate, so no shifting is required. Signed-off-by: Heiko Stuebner Reviewed-by: Conor Dooley --- arch/riscv/include/asm/parse_asm.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/riscv/include/asm/parse_asm.h b/arch/riscv/include/asm/parse_asm.h index c287c1426aa7..939ede0ee527 100644 --- a/arch/riscv/include/asm/parse_asm.h +++ b/arch/riscv/include/asm/parse_asm.h @@ -25,6 +25,15 @@ #define J_IMM_11_MASK GENMASK(0, 0) #define J_IMM_19_12_MASK GENMASK(7, 0) +/* + * U-type IMMs contain the upper 20bits [31:20] of an immediate with + * the rest filled in by zeros, so no shifting required. Similarly, + * bit31 contains the signed state, so no sign extension necessary. + */ +#define U_IMM_SIGN_OPOFF 31 +#define U_IMM_31_12_OPOFF 0 +#define U_IMM_31_12_MASK GENMASK(31, 12) + /* The bit field of immediate value in B-type instruction */ #define B_IMM_SIGN_OPOFF 31 #define B_IMM_10_5_OPOFF 25 @@ -183,6 +192,10 @@ static inline bool is_ ## INSN_NAME ## _insn(long insn) \ #define RV_X(X, s, mask) (((X) >> (s)) & (mask)) #define RVC_X(X, s, mask) RV_X(X, s, mask) +#define EXTRACT_UTYPE_IMM(x) \ + ({typeof(x) x_ = (x); \ + (RV_X(x_, U_IMM_31_12_OPOFF, U_IMM_31_12_MASK)); }) + #define EXTRACT_JTYPE_IMM(x) \ ({typeof(x) x_ = (x); \ (RV_X(x_, J_IMM_10_1_OPOFF, J_IMM_10_1_MASK) << J_IMM_10_1_OFF) | \