From patchwork Wed Nov 16 13:54:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daire McNamara X-Patchwork-Id: 13045247 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B841EC43217 for ; Wed, 16 Nov 2022 13:56:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ou21KtQQbHRLPkfiKQlIGw4PT0mr4771+00NFVEi/cg=; b=Tyrk6uXA9tZbx/ 7lsnz5PB9rnfj8Fk6ANJFeMhvHyte+wzP9JrNO1Yxe6HMaJKFRT3i0bGiDtDlaTuGT0tr/mwawcAR N1qwm59CvyHUHuGFcnVdIfaPb3/YbA4Elgfwwh5w9AXdi3Q9gOodp3KwpedrREzw+DfkkiBCPllmf 8fzY2I1J+yjtLzV8KAhSwOWftACBoR2WU/+YxImpgDenJW9JzlPWxZAqcCE1MaIVRKQdJ3kGaANp/ WDCqPr3IJw4kbt1cwSDrArwXoqOTHdErSqdTfuNTvpyS5eykQLtcCVxpjP53yH2kbwfm6g2tjQ05a 9n+BPXWlfWkj0Jp9vOsQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ovItR-004Jg9-5B; Wed, 16 Nov 2022 13:55:57 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ovIsz-004JQS-9l for linux-riscv@lists.infradead.org; Wed, 16 Nov 2022 13:55:32 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1668606929; x=1700142929; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LQ9aw0MjTD+DyTb5ONZF9JuB5bkGwJGyd3a6rEfBHMU=; b=ZU9s1AJHwIa07nPegMiFM253gx55aZSgze2S/GgHDGRkVn8rHfqR0kOF 7Mkg/fqiNzLWrE43xjuXXIMomF60B0wuXy/jrfp2D46Mu9YfNB31di5sq +lWOV2mTPDVcPDjJkMXHQXt+JKGzDg3xZDwfCLGglImSejHPLkPIMZuqi swwNdHMlSuqr8YzCR64VA/wToHqYOlQqSMQ2sLwEXGmEkLpT46vr6YVsY /0fULRHnVU/EmQHE7ZQodZk5duJgRPy61CXnT8pS4G3ZPkvgx0vl/MZwx J6DtBNPr4PEXvI8r5A/Hulv50AdsnwK5YBme/0H0jXSMiWL0DWAiuVVv5 A==; X-IronPort-AV: E=Sophos;i="5.96,167,1665471600"; d="scan'208";a="123709426" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Nov 2022 06:55:27 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Wed, 16 Nov 2022 06:55:21 -0700 Received: from daire-X570.amer.actel.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Wed, 16 Nov 2022 06:55:19 -0700 From: To: , , , , , , , , , , , CC: Daire McNamara Subject: [PATCH v1 3/9] PCI: microchip: Enable event handlers to access bridge and ctrl ptrs Date: Wed, 16 Nov 2022 13:54:58 +0000 Message-ID: <20221116135504.258687-4-daire.mcnamara@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221116135504.258687-1-daire.mcnamara@microchip.com> References: <20221116135504.258687-1-daire.mcnamara@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221116_055529_488677_9A32517B X-CRM114-Status: UNSURE ( 7.98 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Daire McNamara Minor re-organisation so that event handlers can access both a pointer to the bridge area of the PCIe rootport and the ctrl area of the PCIe rootport. Signed-off-by: Daire McNamara Signed-off-by: Conor Dooley Reviewed-by: Conor Dooley --- drivers/pci/controller/pcie-microchip-host.c | 31 ++++++++++---------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c index 30153fd1a2b3..a81e6d25e347 100644 --- a/drivers/pci/controller/pcie-microchip-host.c +++ b/drivers/pci/controller/pcie-microchip-host.c @@ -654,9 +654,10 @@ static inline u32 reg_to_event(u32 reg, struct event_map field) return (reg & field.reg_mask) ? BIT(field.event_bit) : 0; } -static u32 pcie_events(void __iomem *addr) +static u32 pcie_events(struct mc_pcie *port) { - u32 reg = readl_relaxed(addr); + void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; + u32 reg = readl_relaxed(ctrl_base_addr + PCIE_EVENT_INT); u32 val = 0; int i; @@ -666,9 +667,10 @@ static u32 pcie_events(void __iomem *addr) return val; } -static u32 sec_errors(void __iomem *addr) +static u32 sec_errors(struct mc_pcie *port) { - u32 reg = readl_relaxed(addr); + void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; + u32 reg = readl_relaxed(ctrl_base_addr + SEC_ERROR_INT); u32 val = 0; int i; @@ -678,9 +680,10 @@ static u32 sec_errors(void __iomem *addr) return val; } -static u32 ded_errors(void __iomem *addr) +static u32 ded_errors(struct mc_pcie *port) { - u32 reg = readl_relaxed(addr); + void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; + u32 reg = readl_relaxed(ctrl_base_addr + DED_ERROR_INT); u32 val = 0; int i; @@ -690,9 +693,10 @@ static u32 ded_errors(void __iomem *addr) return val; } -static u32 local_events(void __iomem *addr) +static u32 local_events(struct mc_pcie *port) { - u32 reg = readl_relaxed(addr); + void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; + u32 reg = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); u32 val = 0; int i; @@ -704,15 +708,12 @@ static u32 local_events(void __iomem *addr) static u32 get_events(struct mc_pcie *port) { - void __iomem *bridge_base_addr = - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; - void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; u32 events = 0; - events |= pcie_events(ctrl_base_addr + PCIE_EVENT_INT); - events |= sec_errors(ctrl_base_addr + SEC_ERROR_INT); - events |= ded_errors(ctrl_base_addr + DED_ERROR_INT); - events |= local_events(bridge_base_addr + ISTATUS_LOCAL); + events |= pcie_events(port); + events |= sec_errors(port); + events |= ded_errors(port); + events |= local_events(port); return events; }