| Message ID | 20221128102632.435174-9-heiko@sntech.de (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Palmer Dabbelt |
| Headers | show |
| Series | Zbb string optimizations and call support in alternatives | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/tree_selection | fail | Guessing tree name failed |
On Mon, Nov 28, 2022 at 11:26:27AM +0100, Heiko Stuebner wrote: > From: Heiko Stuebner <heiko.stuebner@vrull.eu> > > RISC-V: add U-type imm parsing to parse_asm header Ditto. > Similar to other existing types, allow extracting the immediate > for a U-type instruction. > > U-type immediates are special in that regard, that the value > in the instruction in bits [31:12] already represents the same > bits of the immediate, so no shifting is required. > > Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> How is this different to the patch I left an R-b for on v1? It doesn't look different, so Reviewed-by: Conor Dooley <conor.dooley@microchip.com> ? > --- > arch/riscv/include/asm/insn.h | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h > index f10cb0fdfa96..1caed8fe5204 100644 > --- a/arch/riscv/include/asm/insn.h > +++ b/arch/riscv/include/asm/insn.h > @@ -34,6 +34,15 @@ > #define RV_J_IMM_11_MASK GENMASK(0, 0) > #define RV_J_IMM_19_12_MASK GENMASK(7, 0) > > +/* > + * U-type IMMs contain the upper 20bits [31:20] of an immediate with > + * the rest filled in by zeros, so no shifting required. Similarly, > + * bit31 contains the signed state, so no sign extension necessary. > + */ > +#define RV_U_IMM_SIGN_OPOFF 31 > +#define RV_U_IMM_31_12_OPOFF 0 > +#define RV_U_IMM_31_12_MASK GENMASK(31, 12) > + > /* The bit field of immediate value in B-type instruction */ > #define RV_B_IMM_SIGN_OPOFF 31 > #define RV_B_IMM_10_5_OPOFF 25 > @@ -235,6 +244,10 @@ static __always_inline bool riscv_insn_is_branch(u32 code) > #define RV_X(X, s, mask) (((X) >> (s)) & (mask)) > #define RVC_X(X, s, mask) RV_X(X, s, mask) > > +#define RV_EXTRACT_UTYPE_IMM(x) \ > + ({typeof(x) x_ = (x); \ > + (RV_X(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); }) > + > #define RV_EXTRACT_JTYPE_IMM(x) \ > ({typeof(x) x_ = (x); \ > (RV_X(x_, RV_J_IMM_10_1_OPOFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OFF) | \ > -- > 2.35.1 >
On Mon, Nov 28, 2022 at 11:26:27AM +0100, Heiko Stuebner wrote: > From: Heiko Stuebner <heiko.stuebner@vrull.eu> > > Similar to other existing types, allow extracting the immediate > for a U-type instruction. > > U-type immediates are special in that regard, that the value > in the instruction in bits [31:12] already represents the same > bits of the immediate, so no shifting is required. > > Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> > --- > arch/riscv/include/asm/insn.h | 13 +++++++++++++ > 1 file changed, 13 insertions(+) With the s/parse_asm/insn/ <<<$SUBJECT that Conor pointed out. Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Am Mittwoch, 30. November 2022, 00:38:32 CET schrieb Conor Dooley: > On Mon, Nov 28, 2022 at 11:26:27AM +0100, Heiko Stuebner wrote: > > From: Heiko Stuebner <heiko.stuebner@vrull.eu> > > > > RISC-V: add U-type imm parsing to parse_asm header > > Ditto. > > > Similar to other existing types, allow extracting the immediate > > for a U-type instruction. > > > > U-type immediates are special in that regard, that the value > > in the instruction in bits [31:12] already represents the same > > bits of the immediate, so no shifting is required. > > > > Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> > > How is this different to the patch I left an R-b for on v1? Somehow with having changed so much for v2, it felt strange carrying over many of the R-b-s. Though yeah, this one could've made it :-) Heiko
On Wed, Nov 30, 2022 at 08:27:47PM +0100, Heiko Stübner wrote: > Am Mittwoch, 30. November 2022, 00:38:32 CET schrieb Conor Dooley: > > On Mon, Nov 28, 2022 at 11:26:27AM +0100, Heiko Stuebner wrote: > > > From: Heiko Stuebner <heiko.stuebner@vrull.eu> > > > > > > RISC-V: add U-type imm parsing to parse_asm header > > > > Ditto. > > > > > Similar to other existing types, allow extracting the immediate > > > for a U-type instruction. > > > > > > U-type immediates are special in that regard, that the value > > > in the instruction in bits [31:12] already represents the same > > > bits of the immediate, so no shifting is required. > > > > > > Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> > > > > How is this different to the patch I left an R-b for on v1? > > Somehow with having changed so much for v2, it felt strange carrying > over many of the R-b-s. Though yeah, this one could've made it :-) Yah, hard to know what to do.. Worth mentioning it explicitly though I think if you do drop tags so that people know where they stand.
diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h index f10cb0fdfa96..1caed8fe5204 100644 --- a/arch/riscv/include/asm/insn.h +++ b/arch/riscv/include/asm/insn.h @@ -34,6 +34,15 @@ #define RV_J_IMM_11_MASK GENMASK(0, 0) #define RV_J_IMM_19_12_MASK GENMASK(7, 0) +/* + * U-type IMMs contain the upper 20bits [31:20] of an immediate with + * the rest filled in by zeros, so no shifting required. Similarly, + * bit31 contains the signed state, so no sign extension necessary. + */ +#define RV_U_IMM_SIGN_OPOFF 31 +#define RV_U_IMM_31_12_OPOFF 0 +#define RV_U_IMM_31_12_MASK GENMASK(31, 12) + /* The bit field of immediate value in B-type instruction */ #define RV_B_IMM_SIGN_OPOFF 31 #define RV_B_IMM_10_5_OPOFF 25 @@ -235,6 +244,10 @@ static __always_inline bool riscv_insn_is_branch(u32 code) #define RV_X(X, s, mask) (((X) >> (s)) & (mask)) #define RVC_X(X, s, mask) RV_X(X, s, mask) +#define RV_EXTRACT_UTYPE_IMM(x) \ + ({typeof(x) x_ = (x); \ + (RV_X(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); }) + #define RV_EXTRACT_JTYPE_IMM(x) \ ({typeof(x) x_ = (x); \ (RV_X(x_, RV_J_IMM_10_1_OPOFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OFF) | \