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Fri, 20 Jan 2023 15:10:31 +0100 (CET) X-Virus-Scanned: E-securemail Secumail-id: <12328.63caa0d8.a1508.0> DKIM-Filter: OpenDKIM Filter v2.10.3 zimbra2.kalray.eu 2144827E043A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kalray.eu; s=32AE1B44-9502-11E5-BA35-3734643DEF29; t=1674223832; bh=Mmv6n5fjDahaZPf9nXXTjzf80aTW/zpMRJ3EQiPoUdY=; h=From:To:Date:Message-Id:MIME-Version; b=p6WlefvsosVHgbuzkRjVnAAQf6mQa5rqWTmqWWRlZqKx1F/YzkuMyWptweWcwaDLB 34rlCsW27s/ilBK/ZzmIj+l9DB+Uq85phZDztQ3g2/btIzaiS3qCm1vV3BnXS+GDT4 annv82J/VXktfKBu+c/t3f6opUH247PXj8+5Ksl8= From: Yann Sionneau To: Arnd Bergmann , Jonathan Corbet , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Will Deacon , Peter Zijlstra , Boqun Feng , Mark Rutland , Eric Biederman , Kees Cook , Oleg Nesterov , Ingo Molnar , Waiman Long , "Aneesh Kumar K.V" , Andrew Morton , Nick Piggin , Paul Moore , Eric Paris , Christian Brauner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jules Maselbas , Yann Sionneau , Guillaume Thouvenin , Clement Leger , Vincent Chardon , Marc =?utf-8?b?UG91bGhp?= =?utf-8?b?w6hz?= , Julian Vetter , Samuel Jones , Ashley Lesdalons , Thomas Costis , Marius Gligor , Jonathan Borne , Julien Villette , Luc Michel , Louis Morhet , Julien Hascoet , Jean-Christophe Pince , Guillaume Missonnier , Alex Michon , Huacai Chen , WANG Xuerui , Shaokun Zhang , John Garry , Guangbin Huang , Bharat Bhushan , Bibo Mao , Atish Patra , "Jason A. Donenfeld" , Qi Liu , Jiaxun Yang , Catalin Marinas , Mark Brown , Janosch Frank , Alexey Dobriyan Cc: Benjamin Mugnier , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-audit@redhat.com, linux-riscv@lists.infradead.org, bpf@vger.kernel.org Subject: [RFC PATCH v2 16/31] irqchip: Add irq-kvx-itgen driver Date: Fri, 20 Jan 2023 15:09:47 +0100 Message-ID: <20230120141002.2442-17-ysionneau@kalray.eu> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230120141002.2442-1-ysionneau@kalray.eu> References: <20230120141002.2442-1-ysionneau@kalray.eu> MIME-Version: 1.0 X-ALTERMIMEV2_out: done X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230120_141016_440315_50E8609B X-CRM114-Status: GOOD ( 31.82 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Jules Maselbas The Kalray Core Interrupt Controller is tightly integrated in each kv3 core present in the Coolidge SoC. It provides the following features: - 32 independent interrupt sources - 2-bit configurable priority level - 2-bit configurable ownership level Co-developed-by: Clement Leger Signed-off-by: Clement Leger Co-developed-by: Julian Vetter Signed-off-by: Julian Vetter Co-developed-by: Vincent Chardon Signed-off-by: Vincent Chardon Signed-off-by: Jules Maselbas Signed-off-by: Yann Sionneau --- Notes: V1 -> V2: new patch - removed header include/linux/irqchip/irq-kvx-apic-gic.h - header moved to drivers/irqchip/ but in another patch - removed print on probe success drivers/irqchip/Kconfig | 8 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-kvx-itgen.c | 236 ++++++++++++++++++++++++++++++++ 3 files changed, 245 insertions(+) create mode 100644 drivers/irqchip/irq-kvx-itgen.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 2433e4ba0759..546bc611f3f3 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -340,6 +340,14 @@ config KVX_APIC_GIC select IRQ_DOMAIN select IRQ_DOMAIN_HIERARCHY +config KVX_ITGEN + bool + depends on KVX + select GENERIC_IRQ_IPI if SMP + select GENERIC_MSI_IRQ_DOMAIN + select IRQ_DOMAIN + select IRQ_DOMAIN_HIERARCHY + config INGENIC_IRQ bool depends on MACH_INGENIC diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 8ac1dd880420..6b8f459d8a21 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -70,6 +70,7 @@ obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o obj-$(CONFIG_MIPS_GIC) += irq-mips-gic.o obj-$(CONFIG_KVX_APIC_GIC) += irq-kvx-apic-gic.o +obj-$(CONFIG_KVX_ITGEN) += irq-kvx-itgen.o obj-$(CONFIG_ARCH_MEDIATEK) += irq-mtk-sysirq.o irq-mtk-cirq.o obj-$(CONFIG_ARCH_DIGICOLOR) += irq-digicolor.o obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o diff --git a/drivers/irqchip/irq-kvx-itgen.c b/drivers/irqchip/irq-kvx-itgen.c new file mode 100644 index 000000000000..f6af023a689e --- /dev/null +++ b/drivers/irqchip/irq-kvx-itgen.c @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2023 Kalray Inc. + * Author(s): Clement Leger + * Julian Vetter + * Vincent Chardon + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Parameters */ +#define KVX_ITGEN_PARAM_OFFSET 0x1100 +#define KVX_ITGEN_PARAM_IT_NUM_OFFSET 0x0 + +/* Target configuration */ +#define KVX_ITGEN_CFG_ENABLE_OFFSET 0x8 +#define KVX_ITGEN_CFG_ELEM_SIZE 0x10 +#define KVX_ITGEN_CFG_TARGET_OFFSET 0x0 +#define KVX_ITGEN_CFG_TARGET_MAILBOX_SHIFT 0x0 +#define KVX_ITGEN_CFG_TARGET_MAILBOX_MASK 0x7FUL +#define KVX_ITGEN_CFG_TARGET_CLUSTER_SHIFT 0x8 +#define KVX_ITGEN_CFG_TARGET_CLUSTER_MASK 0x700UL +#define KVX_ITGEN_CFG_TARGET_SELECT_BIT_SHIFT 0x18 +#define KVX_ITGEN_CFG_TARGET_SELECT_BIT_MASK 0x3F000000UL + +#define MB_ADDR_CLUSTER_SHIFT 24 +#define MB_ADDR_MAILBOX_SHIFT 9 + +/** + * struct kvx_itgen - kvx interrupt generator (MSI client) + * @base: base address of the itgen controller + * @domain: IRQ domain of the controller + * @pdev: Platform device associated to the controller + */ +struct kvx_itgen { + void __iomem *base; + struct irq_domain *domain; + struct platform_device *pdev; +}; + +static void __iomem *get_itgen_cfg_offset(struct kvx_itgen *itgen, + irq_hw_number_t hwirq) +{ + return itgen->base + KVX_ITGEN_CFG_TARGET_OFFSET + + hwirq * KVX_ITGEN_CFG_ELEM_SIZE; +} + +void __iomem *get_itgen_param_offset(struct kvx_itgen *itgen) +{ + return itgen->base + KVX_ITGEN_PARAM_OFFSET; +} + +static void kvx_itgen_enable(struct irq_data *data, u32 value) +{ + struct kvx_itgen *itgen = irq_data_get_irq_chip_data(data); + void __iomem *enable_reg = + get_itgen_cfg_offset(itgen, irqd_to_hwirq(data)) + + KVX_ITGEN_CFG_ENABLE_OFFSET; + + dev_dbg(&itgen->pdev->dev, "%sabling hwirq %d, addr %p\n", + value ? "En" : "Dis", + (int) irqd_to_hwirq(data), + enable_reg); + writel(value, enable_reg); +} + +static void kvx_itgen_mask(struct irq_data *data) +{ + kvx_itgen_enable(data, 0x0); + irq_chip_mask_parent(data); +} + +static void kvx_itgen_unmask(struct irq_data *data) +{ + kvx_itgen_enable(data, 0x1); + irq_chip_unmask_parent(data); +} + +#ifdef CONFIG_SMP +static int kvx_itgen_irq_set_affinity(struct irq_data *data, + const struct cpumask *dest, bool force) +{ + return -ENOSYS; +} +#endif + +static struct irq_chip itgen_irq_chip = { + .name = "kvx-itgen", + .irq_mask = kvx_itgen_mask, + .irq_unmask = kvx_itgen_unmask, +#ifdef CONFIG_SMP + .irq_set_affinity = kvx_itgen_irq_set_affinity, +#endif +}; + +#define ITGEN_UNSUPPORTED_TYPES (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING) + +static int kvx_itgen_domain_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *args) +{ + int i, err; + struct irq_fwspec *fwspec = args; + int hwirq = fwspec->param[0]; + int type = IRQ_TYPE_NONE; + struct kvx_itgen *itgen; + + if (fwspec->param_count >= 2) + type = fwspec->param[1]; + + WARN_ON(type & ITGEN_UNSUPPORTED_TYPES); + + err = platform_msi_device_domain_alloc(domain, virq, nr_irqs); + if (err) + return err; + + itgen = platform_msi_get_host_data(domain); + + for (i = 0; i < nr_irqs; i++) { + irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, + &itgen_irq_chip, itgen); + if (type == IRQ_TYPE_LEVEL_HIGH) + irq_set_handler(virq + i, handle_level_irq); + } + + return 0; +} + +static const struct irq_domain_ops itgen_domain_ops = { + .alloc = kvx_itgen_domain_alloc, + .free = irq_domain_free_irqs_common, +}; + +static void kvx_itgen_write_msg(struct msi_desc *desc, struct msi_msg *msg) +{ + struct irq_data *d = irq_get_irq_data(desc->irq); + struct kvx_itgen *itgen = irq_data_get_irq_chip_data(d); + uint32_t cfg_val = 0; + uintptr_t dest_addr = ((uint64_t) msg->address_hi << 32) | + msg->address_lo; + void __iomem *cfg = get_itgen_cfg_offset(itgen, irqd_to_hwirq(d)); + + /* + * Address in the msi data is the address of the targeted mailbox. + * To save a few cells of hw, itgen configuration expects the target + * of the write using mppa id, cluster id and mailbox id instead + * of address. + * We extract these informations from the mailbox address. + */ + + cfg_val |= (((kvx_sfr_get(PCR) & KVX_SFR_PCR_CID_MASK) >> + KVX_SFR_PCR_CID_SHIFT) + << KVX_ITGEN_CFG_TARGET_CLUSTER_SHIFT); + cfg_val |= ((dest_addr >> MB_ADDR_MAILBOX_SHIFT) & + KVX_ITGEN_CFG_TARGET_MAILBOX_MASK) + << KVX_ITGEN_CFG_TARGET_MAILBOX_SHIFT; + + /* + * msg->data contains the bit number to be written and is included in + * the itgen config + */ + cfg_val |= ((msg->data << KVX_ITGEN_CFG_TARGET_SELECT_BIT_SHIFT) + & KVX_ITGEN_CFG_TARGET_SELECT_BIT_MASK); + + dev_dbg(&itgen->pdev->dev, + "Writing dest_addr %lx, value %x to cfg %p\n", + dest_addr, cfg_val, cfg); + + writel(cfg_val, cfg); +} + +static int +kvx_itgen_device_probe(struct platform_device *pdev) +{ + struct kvx_itgen *itgen; + u32 it_count; + struct resource *mem; + + itgen = devm_kzalloc(&pdev->dev, sizeof(*itgen), GFP_KERNEL); + if (!itgen) + return -ENOMEM; + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + itgen->base = devm_ioremap_resource(&pdev->dev, mem); + if (IS_ERR(itgen->base)) { + dev_err(&pdev->dev, "Failed to ioremap itgen\n"); + return PTR_ERR(itgen->base); + } + + itgen->pdev = pdev; + it_count = readl(get_itgen_param_offset(itgen) + + KVX_ITGEN_PARAM_IT_NUM_OFFSET); + + itgen->domain = platform_msi_create_device_domain(&pdev->dev, + it_count, + kvx_itgen_write_msg, + &itgen_domain_ops, + itgen); + if (!itgen->domain) { + dev_err(&pdev->dev, "Failed to create device domain\n"); + return -ENOMEM; + } + + platform_set_drvdata(pdev, itgen); + + return 0; +} + +static const struct of_device_id itgen_of_match[] = { + { .compatible = "kalray,kvx-itgen" }, + { /* END */ } +}; +MODULE_DEVICE_TABLE(of, itgen_of_match); + +static struct platform_driver itgen_platform_driver = { + .driver = { + .name = "kvx-itgen", + .of_match_table = itgen_of_match, + }, + .probe = kvx_itgen_device_probe, +}; + +static int __init kvx_itgen_init(void) +{ + return platform_driver_register(&itgen_platform_driver); +} + +arch_initcall(kvx_itgen_init);