| Message ID | 20230125142056.18356-7-andy.chiu@sifive.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Palmer Dabbelt |
| Headers | show |
| Series | riscv: Add vector ISA support | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Series has a cover letter |
| conchuod/tree_selection | success | Guessed tree name to be for-next |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 13 and now 13 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/alphanumeric_selects | success | Out of order selects before the patch: 57 and now 57 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 2 this patch: 2 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 23 lines checked |
| conchuod/source_inline | success | Was 0 now: 0 |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
Hey Andy, On Wed, Jan 25, 2023 at 02:20:43PM +0000, Andy Chiu wrote: > These are small and likely to be frequently called so implement as > inline routines (vs. function call). > > Co-developed-by: Guo Ren <guoren@linux.alibaba.com> > Signed-off-by: Guo Ren <guoren@linux.alibaba.com> > Co-developed-by: Vincent Chen <vincent.chen@sifive.com> > Signed-off-by: Vincent Chen <vincent.chen@sifive.com> > Signed-off-by: Greentime Hu <greentime.hu@sifive.com> > Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> > [vineetg: create new patch from meshup, introduced asm variant] > Signed-off-by: Andy Chiu <andy.chiu@sifive.com> > [andy.chiu: remove calls from asm thus remove asm vaiant] Again, these chains are odd but a reflection of the series' history I guess. > --- > arch/riscv/include/asm/vector.h | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h > index 917c8867e702..0fda0faf5277 100644 > --- a/arch/riscv/include/asm/vector.h > +++ b/arch/riscv/include/asm/vector.h > @@ -11,12 +11,23 @@ > #ifdef CONFIG_RISCV_ISA_V > > #include <asm/hwcap.h> > +#include <asm/csr.h> > > static __always_inline bool has_vector(void) > { > return static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_VECTOR]); This likely will need to drop the static branch due to Jisheng's series. See here for what the equivalent change to has_fpu() was: https://lore.kernel.org/all/20230115154953.831-1-jszhang@kernel.org/ Hopefully that series has been queued by the time you are resubmitting this one. > } > > +static __always_inline void rvv_enable(void) I'm not keen on these function names. IMO, they should be riscv_v_{en,dis}able() to match other riscv specific functions, like those of zicbom or sbi stuff. Other parts of this series use riscv_v_foo & riscv_vfoo. Some of the kvm bits spell out vector rather than v. Consistent naming of functions etc would be appreciated. Thanks, Conor.
diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 917c8867e702..0fda0faf5277 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -11,12 +11,23 @@ #ifdef CONFIG_RISCV_ISA_V #include <asm/hwcap.h> +#include <asm/csr.h> static __always_inline bool has_vector(void) { return static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_VECTOR]); } +static __always_inline void rvv_enable(void) +{ + csr_set(CSR_SSTATUS, SR_VS); +} + +static __always_inline void rvv_disable(void) +{ + csr_clear(CSR_SSTATUS, SR_VS); +} + #else /* ! CONFIG_RISCV_ISA_V */ static __always_inline bool has_vector(void) { return false; }