From patchwork Sat Jan 28 17:28:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13119907 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 78EE6C38142 for ; Sat, 28 Jan 2023 17:39:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=M/eNkyPnrOsKu2PLct4XhnqCrRMP1N5HE6YUg0nDrHM=; b=ufsKjgaysaxwMT ZZAqYMvFAIS78Bu9hvZnSVUTuTuCo3BaIv1WTU4wDaQt6ieWXe6N61Or8zSDcHb6N2zX/GTxOzuS/ UxkmzPTyFBmHEHwCKnMptwFVwHLGPahYHNbB1suFcgd0zBPbM6F15Abl/VwQobWRxNLx7h+i2HoYq ftflS8NPzx4iX2lLnIvG5mEbw5sp0axqZa3noo2jMnGG4y0Ye7vBkkw2SWmrMMFjudu1n5Ndty0il 4E24y13GNJNKB+pCRpDffH71TiDky7gZFis6X4AzaywpO/jHL83EbwlRhPkfNy4oF2C/7c1lOoMu9 y7FDXpbb+a35pgit2LyA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pLpB3-000T5r-Lh; Sat, 28 Jan 2023 17:39:45 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pLpAy-000T1L-Vv; Sat, 28 Jan 2023 17:39:43 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 59B24B80B84; Sat, 28 Jan 2023 17:39:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 864F4C433EF; Sat, 28 Jan 2023 17:39:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1674927578; bh=rCPun3SIfwHKigmxd5E5UG5gquIqTtUI/lKy/0NjAL8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=n39vjOjE7PcDBd6PoM+cQWvfzAPYJrF+ge3GNRMBO4LCEyeNcTfWUiW/jq9SRG8u9 XhytVj5GI+UjMOq6Nnh57CDC8jONbJ/GfYKn1saAB+jynibgLpOYejwJhLCeynwnLb A8/m0OC/vVq/0XNESyRqcxdRCZ/WPngdT7ph505pJRrK48xvzAx9dGO6uP+aGxHLZJ bH62WUySDcefzgighgM+NpkCcyyPwJTitiqzbEJ2k/TOLwEyHVTEfTxYOSr0/iIo2a JgCuuWH3QvDGlZEFjILYOcmCoiMA8YswfOMpnAqgjm0AGxsP3RHs0MheQ0d917PhCI 8bAM1id64Br6g== From: Jisheng Zhang To: Palmer Dabbelt , Paul Walmsley , Albert Ou , Anup Patel , Atish Patra , Heiko Stuebner , Andrew Jones , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: [PATCH v5 05/13] riscv: introduce riscv_has_extension_[un]likely() Date: Sun, 29 Jan 2023 01:28:48 +0800 Message-Id: <20230128172856.3814-6-jszhang@kernel.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230128172856.3814-1-jszhang@kernel.org> References: <20230128172856.3814-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230128_093941_371092_CC5FF0B2 X-CRM114-Status: GOOD ( 13.41 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Generally, riscv ISA extensions are fixed for any specific hardware platform, so a hart's features won't change after booting. This chacteristic makes it straightforward to use a static branch to check if a specific ISA extension is supported or not to optimize performance. However, some ISA extensions such as SVPBMT and ZICBOM are handled via. the alternative sequences. Basically, for ease of maintenance, we prefer to use static branches in C code, but recently, Samuel found that the static branch usage in cpu_relax() breaks building with CONFIG_CC_OPTIMIZE_FOR_SIZE[1]. As Samuel pointed out, "Having a static branch in cpu_relax() is problematic because that function is widely inlined, including in some quite complex functions like in the VDSO. A quick measurement shows this static branch is responsible by itself for around 40% of the jump table." Samuel's findings pointed out one of a few downsides of static branches usage in C code to handle ISA extensions detected at boot time: static branch's metadata in the __jump_table section, which is not discarded after ISA extensions are finalized, wastes some space. I want to try to solve the issue for all possible dynamic handling of ISA extensions at boot time. Inspired by Mark[2], this patch introduces riscv_has_extension_*() helpers, which work like static branches but are patched using alternatives, thus the metadata can be freed after patching. Link: https://lore.kernel.org/linux-riscv/20220922060958.44203-1-samuel@sholland.org/ [1] Link: https://lore.kernel.org/linux-arm-kernel/20220912162210.3626215-8-mark.rutland@arm.com/ [2] Signed-off-by: Jisheng Zhang Reviewed-by: Andrew Jones Acked-by: Conor Dooley --- arch/riscv/include/asm/hwcap.h | 37 ++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 8e0ee841fa77..411ef0fb5c4b 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -8,6 +8,7 @@ #ifndef _ASM_RISCV_HWCAP_H #define _ASM_RISCV_HWCAP_H +#include #include #include #include @@ -99,6 +100,42 @@ static __always_inline int riscv_isa_ext2key(int num) } } +static __always_inline bool +riscv_has_extension_likely(const unsigned long ext) +{ + compiletime_assert(ext < RISCV_ISA_EXT_MAX, + "ext must be < RISCV_ISA_EXT_MAX"); + + asm_volatile_goto( + ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1) + : + : [ext] "i" (ext) + : + : l_no); + + return true; +l_no: + return false; +} + +static __always_inline bool +riscv_has_extension_unlikely(const unsigned long ext) +{ + compiletime_assert(ext < RISCV_ISA_EXT_MAX, + "ext must be < RISCV_ISA_EXT_MAX"); + + asm_volatile_goto( + ALTERNATIVE("nop", "j %l[l_yes]", 0, %[ext], 1) + : + : [ext] "i" (ext) + : + : l_yes); + + return false; +l_yes: + return true; +} + unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)