From patchwork Sat Jan 28 17:28:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13119910 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3F540C61DA4 for ; Sat, 28 Jan 2023 17:40:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pootc9ERKNLxu68fB/FqxM2T4ax6xoMd52EnLuj5EZ4=; b=lTLcJkK5YvVqK3 RpWoy+/t4pD5unhhFxkCp5Ur5jVmBV5d45wRG7sVk9PutpcVT9xqEb3+7iUkzc7tIAnhnESm/5Jet f9wz5uByjJodq/cuVcrf7nNWojNWcZj/jgC5vyP0dRypjl5rcRutgYZDflDx3M6DskbqY7mxuKirx bB3pKZe1WAnO2u8uV+VYc+/mHuBY8HKTc9Hw3ju/yFGOGgS/IK8XqyVkYs6kIu1iY1ebeZ1Cu4Gox 3ew9CB4mE/uXiKsxfF42z8ClgL643Z9xrLCSlb3iOaKBjoNBTWDv53YO7Ibqab0WV8TfminhhaNeU EU9Z2hq8Oh5ZG9+vqnJg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pLpBH-000TJk-Dr; Sat, 28 Jan 2023 17:39:59 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pLpB6-000T8I-1V; Sat, 28 Jan 2023 17:39:49 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 9505F60C38; Sat, 28 Jan 2023 17:39:47 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 765F2C433EF; Sat, 28 Jan 2023 17:39:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1674927587; bh=xns7aXEDFfAuJusdRE+rDCll5I8rYO5SpKHZOS1DEIA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TUx+idFX2Ddn8y39dLpOYIR3uwySlB380yNZKygJJdk2Z7Qcef0UUqrgaWnHi7yce t1VuaVAJ0w67kvofeP2LysFz6WSpGaUTnN2Cq4rD40JE+brZ6VDA0yguWGCI4KGt76 OhpNk3k0i2WyOFV2hL058F733HRfkDzyu55HL1/PvEd80e1l3VviiBZb87tjNnqMEB 6+aZPwFBCmzS0oj4mX+Vw6r/WLZh2MVYOmI52NY4l3+GgPkeTZsT8mZKlIfJq14MgL T3XBH6L29NLW5AH4j5l0k78adQV0BgTMcCUA5Ms49SkKJsKOJFAs7QxN4IXLRfgnGK KYzLRE7PUjVjw== From: Jisheng Zhang To: Palmer Dabbelt , Paul Walmsley , Albert Ou , Anup Patel , Atish Patra , Heiko Stuebner , Andrew Jones , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: [PATCH v5 08/13] riscv: module: Add ADD16 and SUB16 rela types Date: Sun, 29 Jan 2023 01:28:51 +0800 Message-Id: <20230128172856.3814-9-jszhang@kernel.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230128172856.3814-1-jszhang@kernel.org> References: <20230128172856.3814-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230128_093948_146770_E8D87327 X-CRM114-Status: UNSURE ( 8.98 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Andrew Jones To prepare for 16-bit relocation types to be emitted in alternatives add support for ADD16 and SUB16. Signed-off-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/kernel/module.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 76f4b9c2ec5b..7c651d55fcbd 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -268,6 +268,13 @@ static int apply_r_riscv_align_rela(struct module *me, u32 *location, return -EINVAL; } +static int apply_r_riscv_add16_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u16 *)location += (u16)v; + return 0; +} + static int apply_r_riscv_add32_rela(struct module *me, u32 *location, Elf_Addr v) { @@ -282,6 +289,13 @@ static int apply_r_riscv_add64_rela(struct module *me, u32 *location, return 0; } +static int apply_r_riscv_sub16_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u16 *)location -= (u16)v; + return 0; +} + static int apply_r_riscv_sub32_rela(struct module *me, u32 *location, Elf_Addr v) { @@ -315,8 +329,10 @@ static int (*reloc_handlers_rela[]) (struct module *me, u32 *location, [R_RISCV_CALL] = apply_r_riscv_call_rela, [R_RISCV_RELAX] = apply_r_riscv_relax_rela, [R_RISCV_ALIGN] = apply_r_riscv_align_rela, + [R_RISCV_ADD16] = apply_r_riscv_add16_rela, [R_RISCV_ADD32] = apply_r_riscv_add32_rela, [R_RISCV_ADD64] = apply_r_riscv_add64_rela, + [R_RISCV_SUB16] = apply_r_riscv_sub16_rela, [R_RISCV_SUB32] = apply_r_riscv_sub32_rela, [R_RISCV_SUB64] = apply_r_riscv_sub64_rela, };