| Message ID | 20230129064956.143664-1-tjytimi@163.com (mailing list archive) |
|---|---|
| State | Rejected |
| Headers | show |
| Series | [v1] riscv: support arch_has_hw_pte_young() | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Single patches do not need cover letters |
| conchuod/tree_selection | success | Guessed tree name to be for-next |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 13 and now 13 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 2014 this patch: 2014 |
| conchuod/alphanumeric_selects | success | Out of order selects before the patch: 57 and now 57 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 2 this patch: 2 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | warning | CHECK: Please use a blank line after function/struct/union/enum declarations |
| conchuod/source_inline | success | Was 0 now: 0 |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On Sun, Jan 29, 2023 at 02:49:56PM +0800, Jinyu Tang wrote: > The arch_has_hw_pte_young() is false for riscv by default. If it's > false, page table walk is almost skipped for MGLRU reclaim. And it > will also cause useless step in __wp_page_copy_user(). > > RISC-V Privileged Book says that riscv have two schemes to manage A > and D bit. > > So add a config for selecting, the default is true. For simple > implementation riscv CPU which just generate page fault, unselect it. > > Signed-off-by: Jinyu Tang <tjytimi@163.com> > --- > arch/riscv/Kconfig | 10 ++++++++++ > arch/riscv/include/asm/pgtable.h | 7 +++++++ > 2 files changed, 17 insertions(+) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index e2b656043abf..17c82885549c 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -180,6 +180,16 @@ config PAGE_OFFSET > default 0x80000000 if 64BIT && !MMU > default 0xff60000000000000 if 64BIT > > +config ARCH_HAS_HARDWARE_PTE_YOUNG > + bool "Hardware Set PTE Access Bit" > + default y > + help > + Select if hardware set A bit when PTE is accessed. The default is > + 'Y', because most RISC-V CPU hardware can manage A and D bit. > + But RISC-V may have simple implementation that do not support > + hardware set A bit but only generate page fault, for that case just > + unselect it. > + > config KASAN_SHADOW_OFFSET > hex > depends on KASAN_GENERIC > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h > index 4eba9a98d0e3..1db54ab4e1ba 100644 > --- a/arch/riscv/include/asm/pgtable.h > +++ b/arch/riscv/include/asm/pgtable.h > @@ -532,6 +532,13 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma, > */ > return ptep_test_and_clear_young(vma, address, ptep); > } > +#ifdef CONFIG_ARCH_HAS_HARDWARE_PTE_YOUNG > +#define arch_has_hw_pte_young arch_has_hw_pte_young > +static inline bool arch_has_hw_pte_young(void) > +{ > + return true; > +} > +#endif > > #define pgprot_noncached pgprot_noncached > static inline pgprot_t pgprot_noncached(pgprot_t _prot) > -- > 2.30.2 > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Thanks, drew
On Sun, Jan 29, 2023 at 02:49:56PM +0800, Jinyu Tang wrote: > The arch_has_hw_pte_young() is false for riscv by default. If it's > false, page table walk is almost skipped for MGLRU reclaim. And it > will also cause useless step in __wp_page_copy_user(). > > RISC-V Privileged Book says that riscv have two schemes to manage A > and D bit. > > So add a config for selecting, the default is true. For simple > implementation riscv CPU which just generate page fault, unselect it. > > Signed-off-by: Jinyu Tang <tjytimi@163.com> > --- > arch/riscv/Kconfig | 10 ++++++++++ > arch/riscv/include/asm/pgtable.h | 7 +++++++ > 2 files changed, 17 insertions(+) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index e2b656043abf..17c82885549c 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -180,6 +180,16 @@ config PAGE_OFFSET > default 0x80000000 if 64BIT && !MMU > default 0xff60000000000000 if 64BIT > > +config ARCH_HAS_HARDWARE_PTE_YOUNG > + bool "Hardware Set PTE Access Bit" > + default y > + help > + Select if hardware set A bit when PTE is accessed. The default is > + 'Y', because most RISC-V CPU hardware can manage A and D bit. > + But RISC-V may have simple implementation that do not support > + hardware set A bit but only generate page fault, for that case just > + unselect it. Hmm, I am not really sure if this is the right way to go. Should we really be defaulting this option to enabled if there are going to be implementations that do not support it? Thanks, Conor.
On Sun, Jan 29, 2023 at 12:21 PM Jinyu Tang <tjytimi@163.com> wrote: > > The arch_has_hw_pte_young() is false for riscv by default. If it's > false, page table walk is almost skipped for MGLRU reclaim. And it > will also cause useless step in __wp_page_copy_user(). > > RISC-V Privileged Book says that riscv have two schemes to manage A > and D bit. > > So add a config for selecting, the default is true. For simple > implementation riscv CPU which just generate page fault, unselect it. I totally disagree with this approach. Almost all existing RISC-V platforms don't have HW support PTE.A and PTE.D updates. We want the same kernel image to run HW with/without PTE.A and PTE.D updates so kconfig based approach is not going to fly. > > Signed-off-by: Jinyu Tang <tjytimi@163.com> > --- > arch/riscv/Kconfig | 10 ++++++++++ > arch/riscv/include/asm/pgtable.h | 7 +++++++ > 2 files changed, 17 insertions(+) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index e2b656043abf..17c82885549c 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -180,6 +180,16 @@ config PAGE_OFFSET > default 0x80000000 if 64BIT && !MMU > default 0xff60000000000000 if 64BIT > > +config ARCH_HAS_HARDWARE_PTE_YOUNG > + bool "Hardware Set PTE Access Bit" > + default y > + help > + Select if hardware set A bit when PTE is accessed. The default is > + 'Y', because most RISC-V CPU hardware can manage A and D bit. > + But RISC-V may have simple implementation that do not support > + hardware set A bit but only generate page fault, for that case just > + unselect it. > + > config KASAN_SHADOW_OFFSET > hex > depends on KASAN_GENERIC > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h > index 4eba9a98d0e3..1db54ab4e1ba 100644 > --- a/arch/riscv/include/asm/pgtable.h > +++ b/arch/riscv/include/asm/pgtable.h > @@ -532,6 +532,13 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma, > */ > return ptep_test_and_clear_young(vma, address, ptep); > } > +#ifdef CONFIG_ARCH_HAS_HARDWARE_PTE_YOUNG > +#define arch_has_hw_pte_young arch_has_hw_pte_young > +static inline bool arch_has_hw_pte_young(void) > +{ > + return true; Drop the kconfig option ARCH_HAS_HARDWARE_PTE_YOUNG and instead use code patching to return true only when Svadu ISA extension is available in DT ISA string. > +} > +#endif > > #define pgprot_noncached pgprot_noncached > static inline pgprot_t pgprot_noncached(pgprot_t _prot) > -- > 2.30.2 > Regards, Anup
On Mon, Jan 30, 2023 at 03:55:55PM +0530, Anup Patel wrote: > On Sun, Jan 29, 2023 at 12:21 PM Jinyu Tang <tjytimi@163.com> wrote: > > > > The arch_has_hw_pte_young() is false for riscv by default. If it's > > false, page table walk is almost skipped for MGLRU reclaim. And it > > will also cause useless step in __wp_page_copy_user(). > > > > RISC-V Privileged Book says that riscv have two schemes to manage A > > and D bit. > > > > So add a config for selecting, the default is true. For simple > > implementation riscv CPU which just generate page fault, unselect it. > > I totally disagree with this approach. > > Almost all existing RISC-V platforms don't have HW support > PTE.A and PTE.D updates. > > We want the same kernel image to run HW with/without PTE.A > and PTE.D updates so kconfig based approach is not going to > fly. > > > > > Signed-off-by: Jinyu Tang <tjytimi@163.com> > > --- > > arch/riscv/Kconfig | 10 ++++++++++ > > arch/riscv/include/asm/pgtable.h | 7 +++++++ > > 2 files changed, 17 insertions(+) > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > index e2b656043abf..17c82885549c 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -180,6 +180,16 @@ config PAGE_OFFSET > > default 0x80000000 if 64BIT && !MMU > > default 0xff60000000000000 if 64BIT > > > > +config ARCH_HAS_HARDWARE_PTE_YOUNG > > + bool "Hardware Set PTE Access Bit" > > + default y > > + help > > + Select if hardware set A bit when PTE is accessed. The default is > > + 'Y', because most RISC-V CPU hardware can manage A and D bit. > > + But RISC-V may have simple implementation that do not support > > + hardware set A bit but only generate page fault, for that case just > > + unselect it. > > + > > config KASAN_SHADOW_OFFSET > > hex > > depends on KASAN_GENERIC > > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h > > index 4eba9a98d0e3..1db54ab4e1ba 100644 > > --- a/arch/riscv/include/asm/pgtable.h > > +++ b/arch/riscv/include/asm/pgtable.h > > @@ -532,6 +532,13 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma, > > */ > > return ptep_test_and_clear_young(vma, address, ptep); > > } > > +#ifdef CONFIG_ARCH_HAS_HARDWARE_PTE_YOUNG > > > +#define arch_has_hw_pte_young arch_has_hw_pte_young > > +static inline bool arch_has_hw_pte_young(void) > > +{ > > + return true; > > Drop the kconfig option ARCH_HAS_HARDWARE_PTE_YOUNG > and instead use code patching to return true only when Svadu > ISA extension is available in DT ISA string. Indeed. I should have checked if there was an extension for this first. It crossed my mind that we should only be enabling features when the extensions are present, but looking at the privileged manual isn't sufficient to learn about the Svadu extension. I should have checked https://wiki.riscv.org/display/HOME/Specification+Status Anyway, I retract my r-b and agree with Anup. Thanks, drew
On 30 Jan 2023, at 10:49, Andrew Jones <ajones@ventanamicro.com> wrote: > > On Mon, Jan 30, 2023 at 03:55:55PM +0530, Anup Patel wrote: >> On Sun, Jan 29, 2023 at 12:21 PM Jinyu Tang <tjytimi@163.com> wrote: >>> >>> The arch_has_hw_pte_young() is false for riscv by default. If it's >>> false, page table walk is almost skipped for MGLRU reclaim. And it >>> will also cause useless step in __wp_page_copy_user(). >>> >>> RISC-V Privileged Book says that riscv have two schemes to manage A >>> and D bit. >>> >>> So add a config for selecting, the default is true. For simple >>> implementation riscv CPU which just generate page fault, unselect it. >> >> I totally disagree with this approach. >> >> Almost all existing RISC-V platforms don't have HW support >> PTE.A and PTE.D updates. >> >> We want the same kernel image to run HW with/without PTE.A >> and PTE.D updates so kconfig based approach is not going to >> fly. >> >>> >>> Signed-off-by: Jinyu Tang <tjytimi@163.com> >>> --- >>> arch/riscv/Kconfig | 10 ++++++++++ >>> arch/riscv/include/asm/pgtable.h | 7 +++++++ >>> 2 files changed, 17 insertions(+) >>> >>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig >>> index e2b656043abf..17c82885549c 100644 >>> --- a/arch/riscv/Kconfig >>> +++ b/arch/riscv/Kconfig >>> @@ -180,6 +180,16 @@ config PAGE_OFFSET >>> default 0x80000000 if 64BIT && !MMU >>> default 0xff60000000000000 if 64BIT >>> >>> +config ARCH_HAS_HARDWARE_PTE_YOUNG >>> + bool "Hardware Set PTE Access Bit" >>> + default y >>> + help >>> + Select if hardware set A bit when PTE is accessed. The default is >>> + 'Y', because most RISC-V CPU hardware can manage A and D bit. >>> + But RISC-V may have simple implementation that do not support >>> + hardware set A bit but only generate page fault, for that case just >>> + unselect it. >>> + >>> config KASAN_SHADOW_OFFSET >>> hex >>> depends on KASAN_GENERIC >>> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h >>> index 4eba9a98d0e3..1db54ab4e1ba 100644 >>> --- a/arch/riscv/include/asm/pgtable.h >>> +++ b/arch/riscv/include/asm/pgtable.h >>> @@ -532,6 +532,13 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma, >>> */ >>> return ptep_test_and_clear_young(vma, address, ptep); >>> } >>> +#ifdef CONFIG_ARCH_HAS_HARDWARE_PTE_YOUNG >> >>> +#define arch_has_hw_pte_young arch_has_hw_pte_young >>> +static inline bool arch_has_hw_pte_young(void) >>> +{ >>> + return true; >> >> Drop the kconfig option ARCH_HAS_HARDWARE_PTE_YOUNG >> and instead use code patching to return true only when Svadu >> ISA extension is available in DT ISA string. > > Indeed. I should have checked if there was an extension for this > first. It crossed my mind that we should only be enabling features > when the extensions are present, but looking at the privileged manual > isn't sufficient to learn about the Svadu extension. I should have > checked https://wiki.riscv.org/display/HOME/Specification+Status > > Anyway, I retract my r-b and agree with Anup. Svadu is a bit of a mess, for years it’s been legal to implement hardware A/D tracking and such implementations exist (it’s what QEMU has done for many years, and I know of an FPGA-based implementation that does it too), yet RVA20S64 outlaws that by requiring what it calls Ssptead and Svadu gets introduced to re-allow that behaviour gated behind a CSR bit. Jess
Hi Jinyu, It seems like it has been a while since the last release of this patch. Do you have any plans for the patch recently? Or, do you mind sharing any internal progress on the patch? We are starting to work on the Svadu extension of pte A/D bit feature on Linux. Do you find any places where we may potentially work together to get things moving? Also, I am willing to base on top of your work and continue sending the series (by keeping all the credits from the original work) Please let me know if you have any thoughts, thanks :) Regards, Yong-Xuan On Sun, Jan 29, 2023 at 2:53 PM Jinyu Tang <tjytimi@163.com> wrote: > > The arch_has_hw_pte_young() is false for riscv by default. If it's > false, page table walk is almost skipped for MGLRU reclaim. And it > will also cause useless step in __wp_page_copy_user(). > > RISC-V Privileged Book says that riscv have two schemes to manage A > and D bit. > > So add a config for selecting, the default is true. For simple > implementation riscv CPU which just generate page fault, unselect it. > > Signed-off-by: Jinyu Tang <tjytimi@163.com> > --- > arch/riscv/Kconfig | 10 ++++++++++ > arch/riscv/include/asm/pgtable.h | 7 +++++++ > 2 files changed, 17 insertions(+) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index e2b656043abf..17c82885549c 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -180,6 +180,16 @@ config PAGE_OFFSET > default 0x80000000 if 64BIT && !MMU > default 0xff60000000000000 if 64BIT > > +config ARCH_HAS_HARDWARE_PTE_YOUNG > + bool "Hardware Set PTE Access Bit" > + default y > + help > + Select if hardware set A bit when PTE is accessed. The default is > + 'Y', because most RISC-V CPU hardware can manage A and D bit. > + But RISC-V may have simple implementation that do not support > + hardware set A bit but only generate page fault, for that case just > + unselect it. > + > config KASAN_SHADOW_OFFSET > hex > depends on KASAN_GENERIC > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h > index 4eba9a98d0e3..1db54ab4e1ba 100644 > --- a/arch/riscv/include/asm/pgtable.h > +++ b/arch/riscv/include/asm/pgtable.h > @@ -532,6 +532,13 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma, > */ > return ptep_test_and_clear_young(vma, address, ptep); > } > +#ifdef CONFIG_ARCH_HAS_HARDWARE_PTE_YOUNG > +#define arch_has_hw_pte_young arch_has_hw_pte_young > +static inline bool arch_has_hw_pte_young(void) > +{ > + return true; > +} > +#endif > > #define pgprot_noncached pgprot_noncached > static inline pgprot_t pgprot_noncached(pgprot_t _prot) > -- > 2.30.2 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
Hi Yong-Xuan, On 25/08/2023 07:42, Yong-Xuan Wang wrote: > Hi Jinyu, > > It seems like it has been a while since the last release of this patch. Do > you have any plans for the patch recently? Or, do you mind sharing any > internal progress on the patch? > > We are starting to work on the Svadu extension of pte A/D bit feature on > Linux. This task was assigned to me on the RISE kernel spreadsheet, if you indeed take over, I'll change it to your name: any objection? Thanks, Alex > Do you find any places where we may potentially work together to > get things moving? Also, I am willing to base on top of your work and > continue sending the series (by keeping all the credits from the original > work) > > Please let me know if you have any thoughts, thanks :) > > Regards, > Yong-Xuan > > On Sun, Jan 29, 2023 at 2:53 PM Jinyu Tang <tjytimi@163.com> wrote: >> The arch_has_hw_pte_young() is false for riscv by default. If it's >> false, page table walk is almost skipped for MGLRU reclaim. And it >> will also cause useless step in __wp_page_copy_user(). >> >> RISC-V Privileged Book says that riscv have two schemes to manage A >> and D bit. >> >> So add a config for selecting, the default is true. For simple >> implementation riscv CPU which just generate page fault, unselect it. >> >> Signed-off-by: Jinyu Tang <tjytimi@163.com> >> --- >> arch/riscv/Kconfig | 10 ++++++++++ >> arch/riscv/include/asm/pgtable.h | 7 +++++++ >> 2 files changed, 17 insertions(+) >> >> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig >> index e2b656043abf..17c82885549c 100644 >> --- a/arch/riscv/Kconfig >> +++ b/arch/riscv/Kconfig >> @@ -180,6 +180,16 @@ config PAGE_OFFSET >> default 0x80000000 if 64BIT && !MMU >> default 0xff60000000000000 if 64BIT >> >> +config ARCH_HAS_HARDWARE_PTE_YOUNG >> + bool "Hardware Set PTE Access Bit" >> + default y >> + help >> + Select if hardware set A bit when PTE is accessed. The default is >> + 'Y', because most RISC-V CPU hardware can manage A and D bit. >> + But RISC-V may have simple implementation that do not support >> + hardware set A bit but only generate page fault, for that case just >> + unselect it. >> + >> config KASAN_SHADOW_OFFSET >> hex >> depends on KASAN_GENERIC >> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h >> index 4eba9a98d0e3..1db54ab4e1ba 100644 >> --- a/arch/riscv/include/asm/pgtable.h >> +++ b/arch/riscv/include/asm/pgtable.h >> @@ -532,6 +532,13 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma, >> */ >> return ptep_test_and_clear_young(vma, address, ptep); >> } >> +#ifdef CONFIG_ARCH_HAS_HARDWARE_PTE_YOUNG >> +#define arch_has_hw_pte_young arch_has_hw_pte_young >> +static inline bool arch_has_hw_pte_young(void) >> +{ >> + return true; >> +} >> +#endif >> >> #define pgprot_noncached pgprot_noncached >> static inline pgprot_t pgprot_noncached(pgprot_t _prot) >> -- >> 2.30.2 >> >> >> _______________________________________________ >> linux-riscv mailing list >> linux-riscv@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-riscv > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
Hi Alex, On Sat, Aug 26, 2023 at 3:39 AM Alexandre Ghiti <alex@ghiti.fr> wrote: > > Hi Yong-Xuan, > > > On 25/08/2023 07:42, Yong-Xuan Wang wrote: > > Hi Jinyu, > > > > It seems like it has been a while since the last release of this patch. Do > > you have any plans for the patch recently? Or, do you mind sharing any > > internal progress on the patch? > > > > We are starting to work on the Svadu extension of pte A/D bit feature on > > Linux. > > > This task was assigned to me on the RISE kernel spreadsheet, if you > indeed take over, I'll change it to your name: any objection? > > Yes, that's fine with me. Thank you! Regards, Yong-Xuan > Thanks, > > > Alex > > > > Do you find any places where we may potentially work together to > > get things moving? Also, I am willing to base on top of your work and > > continue sending the series (by keeping all the credits from the original > > work) > > > > Please let me know if you have any thoughts, thanks :) > > > > Regards, > > Yong-Xuan > > > > On Sun, Jan 29, 2023 at 2:53 PM Jinyu Tang <tjytimi@163.com> wrote: > >> The arch_has_hw_pte_young() is false for riscv by default. If it's > >> false, page table walk is almost skipped for MGLRU reclaim. And it > >> will also cause useless step in __wp_page_copy_user(). > >> > >> RISC-V Privileged Book says that riscv have two schemes to manage A > >> and D bit. > >> > >> So add a config for selecting, the default is true. For simple > >> implementation riscv CPU which just generate page fault, unselect it. > >> > >> Signed-off-by: Jinyu Tang <tjytimi@163.com> > >> --- > >> arch/riscv/Kconfig | 10 ++++++++++ > >> arch/riscv/include/asm/pgtable.h | 7 +++++++ > >> 2 files changed, 17 insertions(+) > >> > >> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > >> index e2b656043abf..17c82885549c 100644 > >> --- a/arch/riscv/Kconfig > >> +++ b/arch/riscv/Kconfig > >> @@ -180,6 +180,16 @@ config PAGE_OFFSET > >> default 0x80000000 if 64BIT && !MMU > >> default 0xff60000000000000 if 64BIT > >> > >> +config ARCH_HAS_HARDWARE_PTE_YOUNG > >> + bool "Hardware Set PTE Access Bit" > >> + default y > >> + help > >> + Select if hardware set A bit when PTE is accessed. The default is > >> + 'Y', because most RISC-V CPU hardware can manage A and D bit. > >> + But RISC-V may have simple implementation that do not support > >> + hardware set A bit but only generate page fault, for that case just > >> + unselect it. > >> + > >> config KASAN_SHADOW_OFFSET > >> hex > >> depends on KASAN_GENERIC > >> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h > >> index 4eba9a98d0e3..1db54ab4e1ba 100644 > >> --- a/arch/riscv/include/asm/pgtable.h > >> +++ b/arch/riscv/include/asm/pgtable.h > >> @@ -532,6 +532,13 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma, > >> */ > >> return ptep_test_and_clear_young(vma, address, ptep); > >> } > >> +#ifdef CONFIG_ARCH_HAS_HARDWARE_PTE_YOUNG > >> +#define arch_has_hw_pte_young arch_has_hw_pte_young > >> +static inline bool arch_has_hw_pte_young(void) > >> +{ > >> + return true; > >> +} > >> +#endif > >> > >> #define pgprot_noncached pgprot_noncached > >> static inline pgprot_t pgprot_noncached(pgprot_t _prot) > >> -- > >> 2.30.2 > >> > >> > >> _______________________________________________ > >> linux-riscv mailing list > >> linux-riscv@lists.infradead.org > >> http://lists.infradead.org/mailman/listinfo/linux-riscv > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index e2b656043abf..17c82885549c 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -180,6 +180,16 @@ config PAGE_OFFSET default 0x80000000 if 64BIT && !MMU default 0xff60000000000000 if 64BIT +config ARCH_HAS_HARDWARE_PTE_YOUNG + bool "Hardware Set PTE Access Bit" + default y + help + Select if hardware set A bit when PTE is accessed. The default is + 'Y', because most RISC-V CPU hardware can manage A and D bit. + But RISC-V may have simple implementation that do not support + hardware set A bit but only generate page fault, for that case just + unselect it. + config KASAN_SHADOW_OFFSET hex depends on KASAN_GENERIC diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index 4eba9a98d0e3..1db54ab4e1ba 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -532,6 +532,13 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma, */ return ptep_test_and_clear_young(vma, address, ptep); } +#ifdef CONFIG_ARCH_HAS_HARDWARE_PTE_YOUNG +#define arch_has_hw_pte_young arch_has_hw_pte_young +static inline bool arch_has_hw_pte_young(void) +{ + return true; +} +#endif #define pgprot_noncached pgprot_noncached static inline pgprot_t pgprot_noncached(pgprot_t _prot)
The arch_has_hw_pte_young() is false for riscv by default. If it's false, page table walk is almost skipped for MGLRU reclaim. And it will also cause useless step in __wp_page_copy_user(). RISC-V Privileged Book says that riscv have two schemes to manage A and D bit. So add a config for selecting, the default is true. For simple implementation riscv CPU which just generate page fault, unselect it. Signed-off-by: Jinyu Tang <tjytimi@163.com> --- arch/riscv/Kconfig | 10 ++++++++++ arch/riscv/include/asm/pgtable.h | 7 +++++++ 2 files changed, 17 insertions(+)