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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id a5-20020adfeec5000000b002bfae6b17d2sm11708916wrp.55.2023.01.30.04.01.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 04:01:32 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: 'Heiko Stuebner ' , 'Krzysztof Kozlowski ' , 'Anup Patel ' , 'Palmer Dabbelt ' , 'Atish Patra ' , 'Paul Walmsley ' , 'Albert Ou ' , 'Conor Dooley ' , 'Rob Herring ' , 'Jisheng Zhang ' Subject: [PATCH v3 2/6] dt-bindings: riscv: Document cboz-block-size Date: Mon, 30 Jan 2023 13:01:24 +0100 Message-Id: <20230130120128.1349464-3-ajones@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230130120128.1349464-1-ajones@ventanamicro.com> References: <20230130120128.1349464-1-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230130_040134_529656_7A119ED5 X-CRM114-Status: UNSURE ( 9.12 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The Zicboz operation (cbo.zero) operates on a block-size defined for the cpu-core. While we already have the riscv,cbom-block-size property, it only provides the block size for Zicbom operations. Even though it's likely Zicboz and Zicbom will use the same size, that's not specified. Create another property specifically for Zicboz. Cc: Rob Herring Signed-off-by: Andrew Jones Reviewed-by: Conor Dooley Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index c6720764e765..f4ee70f8e1cf 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -72,6 +72,11 @@ properties: description: The blocksize in bytes for the Zicbom cache operations. + riscv,cboz-block-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The blocksize in bytes for the Zicboz cache operations. + riscv,isa: description: Identifies the specific RISC-V instruction set architecture