| Message ID | 20230206201455.1790329-2-evan@rivosinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Palmer Dabbelt |
| Headers | show |
| Series | RISC-V Hardware Probing User Interface | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/tree_selection | fail | Failed to apply to next/pending-fixes or riscv/for-next |
On Mon, Feb 06, 2023 at 12:14:50PM -0800, Evan Green wrote: > In preparation for tracking and exposing microarchitectural details to > userspace (like whether or not unaligned accesses are fast), move the > riscv_cpuinfo struct out to its own new cpufeatures.h header. It will > need to be used by more than just cpu.c. > > Signed-off-by: Evan Green <evan@rivosinc.com> > --- > > (no changes since v1) Really? I don't recall seeing this patch in v1? ;) > > arch/riscv/include/asm/cpufeature.h | 21 +++++++++++++++++++++ > arch/riscv/kernel/cpu.c | 8 ++------ > 2 files changed, 23 insertions(+), 6 deletions(-) > create mode 100644 arch/riscv/include/asm/cpufeature.h > > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h > new file mode 100644 > index 000000000000..66c251d98290 > --- /dev/null > +++ b/arch/riscv/include/asm/cpufeature.h > @@ -0,0 +1,21 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright 2022 Rivos, Inc > + */ > + > +#ifndef _ASM_CPUFEATURE_H > +#define _ASM_CPUFEATURE_H > + > +/* > + * These are probed via a device_initcall(), via either the SBI or directly > + * from the cooresponding CSRs. May as well fix the typo here while we are moving the code & a respin is required anyway. I'm sure we'll need this patch regardless of approach, so: Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Cheers, Conor.
On Tue, Feb 14, 2023 at 1:38 PM Conor Dooley <conor@kernel.org> wrote: > > On Mon, Feb 06, 2023 at 12:14:50PM -0800, Evan Green wrote: > > In preparation for tracking and exposing microarchitectural details to > > userspace (like whether or not unaligned accesses are fast), move the > > riscv_cpuinfo struct out to its own new cpufeatures.h header. It will > > need to be used by more than just cpu.c. > > > > Signed-off-by: Evan Green <evan@rivosinc.com> > > --- > > > > (no changes since v1) > > Really? I don't recall seeing this patch in v1? ;) My bad, that's an artifact of the tool I'm using (patman) to help me with patch formatting. > > > > > arch/riscv/include/asm/cpufeature.h | 21 +++++++++++++++++++++ > > arch/riscv/kernel/cpu.c | 8 ++------ > > 2 files changed, 23 insertions(+), 6 deletions(-) > > create mode 100644 arch/riscv/include/asm/cpufeature.h > > > > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h > > new file mode 100644 > > index 000000000000..66c251d98290 > > --- /dev/null > > +++ b/arch/riscv/include/asm/cpufeature.h > > @@ -0,0 +1,21 @@ > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > +/* > > + * Copyright 2022 Rivos, Inc > > + */ > > + > > +#ifndef _ASM_CPUFEATURE_H > > +#define _ASM_CPUFEATURE_H > > + > > +/* > > + * These are probed via a device_initcall(), via either the SBI or directly > > + * from the cooresponding CSRs. > > May as well fix the typo here while we are moving the code & a respin is > required anyway. Will do. > > I'm sure we'll need this patch regardless of approach, so: > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thank you!
diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h new file mode 100644 index 000000000000..66c251d98290 --- /dev/null +++ b/arch/riscv/include/asm/cpufeature.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2022 Rivos, Inc + */ + +#ifndef _ASM_CPUFEATURE_H +#define _ASM_CPUFEATURE_H + +/* + * These are probed via a device_initcall(), via either the SBI or directly + * from the cooresponding CSRs. + */ +struct riscv_cpuinfo { + unsigned long mvendorid; + unsigned long marchid; + unsigned long mimpid; +}; + +DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); + +#endif diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 1b9a5a66e55a..684e5419d37d 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -7,6 +7,7 @@ #include <linux/init.h> #include <linux/seq_file.h> #include <linux/of.h> +#include <asm/cpufeature.h> #include <asm/csr.h> #include <asm/hwcap.h> #include <asm/sbi.h> @@ -70,12 +71,7 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) return -1; } -struct riscv_cpuinfo { - unsigned long mvendorid; - unsigned long marchid; - unsigned long mimpid; -}; -static DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); +DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); unsigned long riscv_cached_mvendorid(unsigned int cpu_id) {
In preparation for tracking and exposing microarchitectural details to userspace (like whether or not unaligned accesses are fast), move the riscv_cpuinfo struct out to its own new cpufeatures.h header. It will need to be used by more than just cpu.c. Signed-off-by: Evan Green <evan@rivosinc.com> --- (no changes since v1) arch/riscv/include/asm/cpufeature.h | 21 +++++++++++++++++++++ arch/riscv/kernel/cpu.c | 8 ++------ 2 files changed, 23 insertions(+), 6 deletions(-) create mode 100644 arch/riscv/include/asm/cpufeature.h