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Mon, 06 Feb 2023 12:15:30 -0800 (PST) Received: from evan.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id k10-20020a63ab4a000000b004df4fbb9823sm6425079pgp.68.2023.02.06.12.15.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 12:15:30 -0800 (PST) From: Evan Green To: Palmer Dabbelt Cc: Conor Dooley , vineetg@rivosinc.com, heiko@sntech.de, slewis@rivosinc.com, Evan Green , Albert Ou , Andrew Bresticker , Celeste Liu , Guo Ren , Jonathan Corbet , Palmer Dabbelt , Paul Walmsley , dram , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v2 3/6] RISC-V: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_IMA Date: Mon, 6 Feb 2023 12:14:52 -0800 Message-Id: <20230206201455.1790329-4-evan@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230206201455.1790329-1-evan@rivosinc.com> References: <20230206201455.1790329-1-evan@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230206_121531_153507_C5CCFD08 X-CRM114-Status: GOOD ( 17.85 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Palmer Dabbelt We have an implicit set of base behaviors that userspace depends on, which are mostly defined in various ISA specifications. Signed-off-by: Palmer Dabbelt Signed-off-by: Evan Green --- (no changes since v1) Documentation/riscv/hwprobe.rst | 16 ++++++++++++++++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 6 +++++- arch/riscv/kernel/sys_riscv.c | 23 +++++++++++++++++++++++ 4 files changed, 45 insertions(+), 2 deletions(-) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst index 97771090e972..ce186967861f 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -35,3 +35,19 @@ The following keys are defined: specifications. * :RISCV_HWPROBE_KEY_MIMPLID:: Contains the value of :mimplid:, as per the ISA specifications. +* :RISCV_HWPROBE_KEY_BASE_BEHAVIOR:: A bitmask containing the base user-visible + behavior that this kernel supports. The following base user ABIs are defined: + * :RISCV_HWPROBE_BASE_BEHAVIOR_IMA:: Support for rv32ima or rv64ima, as + defined by version 2.2 of the user ISA and version 1.10 of the privileged + ISA, with the following known exceptions (more exceptions may be added, + but only if it can be demonstrated that the user ABI is not broken): + * The :fence.i: instruction cannot be directly executed by userspace + programs (it may still be executed in userspace via a + kernel-controlled mechanism such as the vDSO). +* :RISCV_HWPROBE_KEY_IMA_EXT_0:: A bitmask containing the extensions that are + compatible with the :RISCV_HWPROBE_BASE_BEHAVIOR_IMA: base system behavior. + * :RISCV_HWPROBE_IMA_FD:: The F and D extensions are supported, as defined + by commit cd20cee ("FMIN/FMAX now implement minimumNumber/maximumNumber, + not minNum/maxNum") of the RISC-V ISA manual. + * :RISCV_HWPROBE_IMA_C:: The C extension is supported, as defined by + version 2.2 of the RISC-V ISA manual. diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h index 08d1c3bdd78a..7e52f1e1fe10 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -8,6 +8,6 @@ #include -#define RISCV_HWPROBE_MAX_KEY 2 +#define RISCV_HWPROBE_MAX_KEY 4 #endif diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 591802047460..ce39d6e74103 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -20,6 +20,10 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_MVENDORID 0 #define RISCV_HWPROBE_KEY_MARCHID 1 #define RISCV_HWPROBE_KEY_MIMPID 2 +#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 +#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) +#define RISCV_HWPROBE_KEY_IMA_EXT_0 4 +#define RISCV_HWPROBE_IMA_FD (1 << 0) +#define RISCV_HWPROBE_IMA_C (1 << 1) /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ - #endif diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 868a12384f5a..74e0d72c877d 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -182,6 +183,28 @@ long do_riscv_hwprobe(struct riscv_hwprobe __user *pairs, long pair_count, ret = hwprobe_mid(pairs, key, &cpus); break; + /* + * The kernel already assumes that the base single-letter ISA + * extensions are supported on all harts, and only supports the + * IMA base, so just cheat a bit here and tell that to + * userspace. + */ + case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: + ret = set_hwprobe(pairs, RISCV_HWPROBE_BASE_BEHAVIOR_IMA); + break; + + case RISCV_HWPROBE_KEY_IMA_EXT_0: + { + u64 val = 0; + + if (has_fpu()) + val |= RISCV_HWPROBE_IMA_FD; + if (elf_hwcap & RISCV_ISA_EXT_c) + val |= RISCV_HWPROBE_IMA_C; + ret = set_hwprobe(pairs, val); + } + break; + /* * For forward compatibility, unknown keys don't fail the whole * call, but get their element key set to -1 and value set to 0