From patchwork Tue Mar 7 10:24:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13163112 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 11749C6FD1B for ; Tue, 7 Mar 2023 10:25:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ywzd8JgvbiFsRBSTUJ8oFBmH3fjzVKDLH1vlq53vnpI=; b=aCyflGt0O5/TEp JB8vTQ8hMAW4nxcZW28PnfoHOJevvTB9hANiOACAb6AXZJh5hbWJVkE6r4OAlj1pUU4iEuCDqRojf TssY63LoWmy2ebiEupMrMrMUBYAYhXVjs0IbxTQq7mHTY56wXc809BEuVFpfxQtzUCfYB8WUgz/rU vPXK2dUwRsp1wHzrWbQTEFrT5cSXqoonwEALZI5LzHioHhptNmnQ9WFSH5SuvDuq9qBiAUFWPCshV BuGGlGLx1kqsDuh0knFuXGs+5GgPRShRVth6Xt4r5rhYFoFlv3uBUBTvFO5sv/LWZoGNd64s7+hcS YYjejwTxRuqTGRfRaL+w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pZUVh-00HFFb-TR; Tue, 07 Mar 2023 10:25:33 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pZUVa-00HFAW-O0 for linux-riscv@lists.infradead.org; Tue, 07 Mar 2023 10:25:30 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1678184726; x=1709720726; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qWB3e5tgDGUKCOsNQtNNw5AKYgfS2AJpadcC4RT6yqQ=; b=rTOH6dJOneMFXelocZNGnNvFxyWNOZGL1YG/KP4xR247oRBLf28OypYx 38wlGufuxf1Rpli/NBClWp1gPGxKFz01ukylDy8HOp3/tt6BdSBQRe6Rx SvmhIFV9Ml60+HKFDYmsknF5UK41h83KzluOoi7NCL1qkvLxwlj4/W9sX 09pedx+eA5NgYeIjbjQEQthzShnM1VdQhUALSV/rL5mdfdfovsyqLpKBH mX4ZlYR1jcDZXInI4dwk/nYb06E33SXK58tyEo6RBn4S9rMUvHbUvAky3 MCrnQgkHSIyWmgXMqUkaG4ap6kaM3tL72/OgR2RHevoJi0Zp9/5YYQN9s Q==; X-IronPort-AV: E=Sophos;i="5.98,240,1673938800"; d="scan'208";a="204052299" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Mar 2023 03:25:24 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Tue, 7 Mar 2023 03:25:22 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Tue, 7 Mar 2023 03:25:19 -0700 From: Conor Dooley To: CC: , , Miguel Ojeda , Alex Gaynor , Wedson Almeida Filho , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , "Nathan Chancellor" , Nick Desaulniers , Tom Rix , , , , Subject: [PATCH v1 2/2] RISC-V: enable building 64-bit kernels with rust support Date: Tue, 7 Mar 2023 10:24:41 +0000 Message-ID: <20230307102441.94417-3-conor.dooley@microchip.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230307102441.94417-1-conor.dooley@microchip.com> References: <20230307102441.94417-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2889; i=conor.dooley@microchip.com; h=from:subject; bh=yBD6MNol++6y2HAWMBBaDRLPC5EtLmNC6wyDPXZv0s4=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCnsAs+aOuwTWjpufIiaM2fzp6LVux5wqT1WnRVxQM+mrf5w VINVRykLgxgHg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACZyoI3hf4iJso1T2ZFneoqdb/5bWv Tebv2x8NxSR/1oV4uw6NaiVkaGdwZ6t/Wjz29b8GVH9OWbU7YeKJ5+V+Fi3plvhnYXf5s1sAAA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230307_022527_020825_B5C27814 X-CRM114-Status: GOOD ( 11.40 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Miguel Ojeda The rust modules work on 64-bit RISC-V, with no twiddling required. Select HAVE_RUST and provide the required flags to kbuild so that the modules can be used. The Makefile and Kconfig changes are lifted from work done by Miguel in the Rust-for-Linux tree, hence his authorship. Following the rabbit hole, the Makefile changes originated in a script, created based on config files originally added by Gary, hence his co-authorship. 32-bit is broken in core rust code, so support is limited to 64-bit: ld.lld: error: undefined symbol: __udivdi3 As 64-bit RISC-V is now supported, add it to the arch support table, taking the opportunity to sort the table in alphabetical order. Co-developed-by: Gary Guo Signed-off-by: Gary Guo Signed-off-by: Miguel Ojeda Signed-off-by: Conor Dooley --- While adding RISC-V to the table, I took the chance to re-sort it alphabetically. I didn't think that warranted co-authorship, but given we had an authorship conversation already I am happy to provide one for that... --- Documentation/rust/arch-support.rst | 3 ++- arch/riscv/Kconfig | 1 + arch/riscv/Makefile | 2 ++ 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/rust/arch-support.rst b/Documentation/rust/arch-support.rst index ed7f4f5b3cf15..77765ffd5af41 100644 --- a/Documentation/rust/arch-support.rst +++ b/Documentation/rust/arch-support.rst @@ -15,7 +15,8 @@ support corresponds to ``S`` values in the ``MAINTAINERS`` file. ============ ================ ============================================== Architecture Level of support Constraints ============ ================ ============================================== -``x86`` Maintained ``x86_64`` only. +``riscv`` Maintained ``riscv64`` only. ``um`` Maintained ``x86_64`` only. +``x86`` Maintained ``x86_64`` only. ============ ================ ============================================== diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index c5e42cc376048..c3179b139361f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -114,6 +114,7 @@ config RISCV select HAVE_POSIX_CPU_TIMERS_TASK_WORK select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_RSEQ + select HAVE_RUST if 64BIT select HAVE_STACKPROTECTOR select HAVE_SYSCALL_TRACEPOINTS select IRQ_DOMAIN diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 6203c33789228..950612bf193cf 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -31,6 +31,8 @@ ifeq ($(CONFIG_ARCH_RV64I),y) KBUILD_AFLAGS += -mabi=lp64 KBUILD_LDFLAGS += -melf64lriscv + + KBUILD_RUSTFLAGS += -Ctarget-cpu=generic-rv64 else BITS := 32 UTS_MACHINE := riscv32