| Message ID | 20230406015216.27034-3-minda.chen@starfivetech.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add JH7110 USB and USB PHY driver support | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/tree_selection | fail | Failed to apply to next/pending-fixes or riscv/for-next |
On 06/04/2023 03:52, Minda Chen wrote: > Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding. > PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY. Subject: drop second/last, redundant "document". The "dt-bindings" prefix is already stating that this is documentation. > > Signed-off-by: Minda Chen <minda.chen@starfivetech.com> > --- > .../phy/starfive,jh7110-pcie-phy.yaml | 58 +++++++++++++++++++ > 1 file changed, 58 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml > new file mode 100644 > index 000000000000..1b868f75ddae > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml > @@ -0,0 +1,58 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: StarFive PCIe 2.0 PHY JH7110 Unless you plan to add here more compatibles, but then use enum for compatible, not const. > + > +maintainers: > + - Minda Chen <minda.chen@starfivetech.com> > + > +properties: > + compatible: > + const: starfive,jh7110-pcie-phy > + > + reg: > + maxItems: 1 > + > + "#phy-cells": > + const: 0 > + > + starfive,sys-syscon: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + items: > + - description: phandle to System Register Controller sys_syscon node. > + - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY. No improvements here. > + description: > + The phandle to System Register Controller syscon node and the PHY connect offset > + of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB3 controller. > + > + starfive,stg-syscon: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + items: > + - description: phandle to System Register Controller stg_syscon node. > + - description: PHY mode offset of STG_SYSCONSAIF__SYSCFG register. > + - description: PHY enable for USB offset of STG_SYSCONSAIF__SYSCFG register. No improvements. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml new file mode 100644 index 000000000000..1b868f75ddae --- /dev/null +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive PCIe 2.0 PHY + +maintainers: + - Minda Chen <minda.chen@starfivetech.com> + +properties: + compatible: + const: starfive,jh7110-pcie-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + starfive,sys-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle to System Register Controller sys_syscon node. + - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY. + description: + The phandle to System Register Controller syscon node and the PHY connect offset + of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB3 controller. + + starfive,stg-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle to System Register Controller stg_syscon node. + - description: PHY mode offset of STG_SYSCONSAIF__SYSCFG register. + - description: PHY enable for USB offset of STG_SYSCONSAIF__SYSCFG register. + description: + The phandle to System Register Controller syscon node and the offset + of STG_SYSCONSAIF__SYSCFG register for PCIe PHY. Total 2 regsisters offset. + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@10210000 { + compatible = "starfive,jh7110-pcie-phy"; + reg = <0x10210000 0x10000>; + #phy-cells = <0>; + starfive,sys-syscon = <&sys_syscon 0x18>; + starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>; + };
Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding. PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> --- .../phy/starfive,jh7110-pcie-phy.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml