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Wed, 19 Apr 2023 04:10:33 -0700 (PDT) Received: from x1.hsd1.or.comcast.net ([2601:1c2:1800:f680:eaf2:1d7a:7338:16cb]) by smtp.gmail.com with ESMTPSA id g12-20020a1709026b4c00b001a24cded097sm11180774plt.236.2023.04.19.04.10.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 04:10:32 -0700 (PDT) From: Drew Fustini To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Conor Dooley , Ved Shanbhogue , =?utf-8?q?Kornel_Dul=C4=99ba?= , Adrien Ricciardi , Nicolas Pitre , Fenghua Yu , Reinette Chatre , Babu Moger , Peter Newman , x86@kernel.org, Rob Herring , James Morse Cc: Drew Fustini Subject: [RFC PATCH 16/21] DO_NOT_MERGE soc: add Foobar SoC cache controller driver Date: Wed, 19 Apr 2023 04:11:06 -0700 Message-Id: <20230419111111.477118-17-dfustini@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230419111111.477118-1-dfustini@baylibre.com> References: <20230419111111.477118-1-dfustini@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230419_041033_762476_35710E69 X-CRM114-Status: GOOD ( 17.33 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add example driver for a cache controller that implements CBQRI. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- drivers/soc/foobar/foobar_cbqri_cache.c | 110 ++++++++++++++++++++++++ 1 file changed, 110 insertions(+) create mode 100644 drivers/soc/foobar/foobar_cbqri_cache.c diff --git a/drivers/soc/foobar/foobar_cbqri_cache.c b/drivers/soc/foobar/foobar_cbqri_cache.c new file mode 100644 index 000000000000..e880488243d8 --- /dev/null +++ b/drivers/soc/foobar/foobar_cbqri_cache.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Foobar Systems CBQRI cache controller + */ + +#define pr_fmt(fmt) "foobar-cache: " fmt + +#include +#include +#include + +static const struct of_device_id foobar_cbqri_cache_ids[] = { + { .compatible = "foobar,cache-controller" }, + { } +}; + +static int __init foobar_cbqri_cache_init(void) +{ + struct device_node *np; + int err; + u32 value; + struct cbqri_controller_info *ctrl_info; + + for_each_matching_node(np, foobar_cbqri_cache_ids) { + if (!of_device_is_available(np)) { + of_node_put(np); + continue; + } + + ctrl_info = kzalloc(sizeof(*ctrl_info), GFP_KERNEL); + if (!ctrl_info) + goto err_node_put; + ctrl_info->type = CBQRI_CONTROLLER_TYPE_CAPACITY; + + err = of_property_read_u32_index(np, "reg", 1, &value); + if (err) { + pr_err("Failed to read reg base address (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->addr = value; + + err = of_property_read_u32_index(np, "reg", 3, &value); + if (err) { + pr_err("Failed to read reg size (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->size = value; + + err = of_property_read_u32(np, "cache-level", &value); + if (err) { + pr_err("Failed to read cache level (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->cache.cache_level = value; + + err = of_property_read_u32(np, "cache-size", &value); + if (err) { + pr_err("Failed to read cache size (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->cache.cache_size = value; + + err = of_property_read_u32(np, "riscv,cbqri-rcid", &value); + if (err) { + pr_err("Failed to read RCID count (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->rcid_count = value; + + err = of_property_read_u32(np, "riscv,cbqri-mcid", &value); + if (err) { + pr_err("Failed to read MCID count (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->mcid_count = value; + + /* + * For CBQRI, any cpu (technically a hart in RISC-V terms) + * can access the memory-mapped registers of any CBQRI + * controller in the system. Therefore, set the CPU mask + * to 'FF' to allow all 8 cores in the example Foobar SoC + */ + err = cpumask_parse("FF", &ctrl_info->cache.cpu_mask); + if (err) { + pr_err("Failed to convert cores mask string to cpumask (%d)", err); + goto err_kfree_ctrl_info; + } + + of_node_put(np); + + pr_debug("addr=0x%lx max-rcid=%u max-mcid=%u level=%d size=%u", + ctrl_info->addr, ctrl_info->rcid_count, ctrl_info->mcid_count, + ctrl_info->cache.cache_level, ctrl_info->cache.cache_size); + + /* Fill the list shared with RISC-V QoS resctrl */ + INIT_LIST_HEAD(&ctrl_info->list); + list_add_tail(&ctrl_info->list, &cbqri_controllers); + } + + return 0; + +err_kfree_ctrl_info: + kfree(ctrl_info); + +err_node_put: + of_node_put(np); + + return err; +} +device_initcall(foobar_cbqri_cache_init);