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Wed, 19 Apr 2023 15:17:49 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id jn11-20020a170903050b00b00196807b5189sm11619190plb.292.2023.04.19.15.17.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 15:17:49 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Alexandre Ghiti , Andrew Jones , Andrew Morton , Anup Patel , Atish Patra , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Suzuki K Poulose , Will Deacon , Marc Zyngier , Sean Christopherson , linux-coco@lists.linux.dev, Dylan Reid , abrestic@rivosinc.com, Samuel Ortiz , Christoph Hellwig , Conor Dooley , Greg Kroah-Hartman , Guo Ren , Heiko Stuebner , Jiri Slaby , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, Mayuresh Chitale , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Rajnesh Kanwal , Uladzislau Rezki Subject: [RFC 09/48] RISC-V: KVM: Add CoVE related nacl helpers Date: Wed, 19 Apr 2023 15:16:37 -0700 Message-Id: <20230419221716.3603068-10-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230419221716.3603068-1-atishp@rivosinc.com> References: <20230419221716.3603068-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230419_231752_749930_64E4AED7 X-CRM114-Status: UNSURE ( 9.82 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The NACL SBI extension allows the scratch area to be customizable per SBI extension. As per the COVH SBI extension, the scratch area stores the guest gpr state. Add some helpers to read/write gprs easily. Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_cove_sbi.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/riscv/include/asm/kvm_cove_sbi.h b/arch/riscv/include/asm/kvm_cove_sbi.h index 24562df..df7d88c 100644 --- a/arch/riscv/include/asm/kvm_cove_sbi.h +++ b/arch/riscv/include/asm/kvm_cove_sbi.h @@ -17,6 +17,21 @@ #include #include +#include + +/** + * CoVE SBI extensions defines the NACL scratch memory. + * uint64_t gprs[32] + * uint64_t reserved[224] + */ +#define get_scratch_gpr_offset(goffset) (goffset - KVM_ARCH_GUEST_ZERO) + +#define nacl_shmem_gpr_write_cove(__s, __g, __o) \ + nacl_shmem_scratch_write_long(__s, get_scratch_gpr_offset(__g), __o) + +#define nacl_shmem_gpr_read_cove(__s, __g) \ + nacl_shmem_scratch_read_long(__s, get_scratch_gpr_offset(__g)) + int sbi_covh_tsm_get_info(struct sbi_cove_tsm_info *tinfo_addr); int sbi_covh_tvm_initiate_fence(unsigned long tvmid); int sbi_covh_tsm_initiate_fence(void);