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Wed, 19 Apr 2023 15:18:02 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id jn11-20020a170903050b00b00196807b5189sm11619190plb.292.2023.04.19.15.18.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 15:18:02 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Alexandre Ghiti , Andrew Jones , Andrew Morton , Anup Patel , Atish Patra , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Suzuki K Poulose , Will Deacon , Marc Zyngier , Sean Christopherson , linux-coco@lists.linux.dev, Dylan Reid , abrestic@rivosinc.com, Samuel Ortiz , Christoph Hellwig , Conor Dooley , Greg Kroah-Hartman , Guo Ren , Heiko Stuebner , Jiri Slaby , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, Mayuresh Chitale , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Rajnesh Kanwal , Uladzislau Rezki Subject: [RFC 15/48] RISC-V: KVM: Add a helper function to trigger fence ops Date: Wed, 19 Apr 2023 15:16:43 -0700 Message-Id: <20230419221716.3603068-16-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230419221716.3603068-1-atishp@rivosinc.com> References: <20230419221716.3603068-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230419_231805_388629_4A94850A X-CRM114-Status: GOOD ( 16.82 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org When Cove is enabled in RISC-V, the TLB shootdown happens in co-ordination with TSM. The host must not issue hfence directly. It relies on TSM to do that instead. It just needs to initiate the process and make sure that all the running vcpus exit the guest mode. As a result, it traps to TSM and TSM issues hfence on behalf of the host. Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_cove.h | 2 ++ arch/riscv/kvm/cove.c | 36 +++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/arch/riscv/include/asm/kvm_cove.h b/arch/riscv/include/asm/kvm_cove.h index 4ea1df1..fc8633d 100644 --- a/arch/riscv/include/asm/kvm_cove.h +++ b/arch/riscv/include/asm/kvm_cove.h @@ -130,6 +130,8 @@ void kvm_riscv_cove_vcpu_switchto(struct kvm_vcpu *vcpu, struct kvm_cpu_trap *tr int kvm_riscv_cove_vm_measure_pages(struct kvm *kvm, struct kvm_riscv_cove_measure_region *mr); int kvm_riscv_cove_vm_add_memreg(struct kvm *kvm, unsigned long gpa, unsigned long size); int kvm_riscv_cove_gstage_map(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned long hva); +/* Fence related function */ +int kvm_riscv_cove_tvm_fence(struct kvm_vcpu *vcpu); #else static inline bool kvm_riscv_cove_enabled(void) {return false; }; static inline int kvm_riscv_cove_init(void) { return -1; } diff --git a/arch/riscv/kvm/cove.c b/arch/riscv/kvm/cove.c index 5b4d9ba..4efcae3 100644 --- a/arch/riscv/kvm/cove.c +++ b/arch/riscv/kvm/cove.c @@ -78,6 +78,42 @@ static int kvm_riscv_cove_fence(void) return rc; } +int kvm_riscv_cove_tvm_fence(struct kvm_vcpu *vcpu) +{ + struct kvm *kvm = vcpu->kvm; + struct kvm_cove_tvm_context *tvmc = kvm->arch.tvmc; + DECLARE_BITMAP(vcpu_mask, KVM_MAX_VCPUS); + unsigned long i; + struct kvm_vcpu *temp_vcpu; + int ret; + + if (!tvmc) + return -EINVAL; + + spin_lock(&tvmc->tvm_fence_lock); + ret = sbi_covh_tvm_initiate_fence(tvmc->tvm_guest_id); + if (ret) { + spin_unlock(&tvmc->tvm_fence_lock); + return ret; + } + + bitmap_clear(vcpu_mask, 0, KVM_MAX_VCPUS); + kvm_for_each_vcpu(i, temp_vcpu, kvm) { + if (temp_vcpu != vcpu) + bitmap_set(vcpu_mask, i, 1); + } + + /* + * The host just needs to make sure that the running vcpus exit the + * guest mode and traps into TSM so that it can issue hfence. + */ + kvm_make_vcpus_request_mask(kvm, KVM_REQ_OUTSIDE_GUEST_MODE, vcpu_mask); + spin_unlock(&tvmc->tvm_fence_lock); + + return 0; +} + + static int cove_convert_pages(unsigned long phys_addr, unsigned long npages, bool fence) { int rc;