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Wed, 19 Apr 2023 15:18:17 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id jn11-20020a170903050b00b00196807b5189sm11619190plb.292.2023.04.19.15.18.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 15:18:17 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Rajnesh Kanwal , Alexandre Ghiti , Andrew Jones , Andrew Morton , Anup Patel , Atish Patra , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Suzuki K Poulose , Will Deacon , Marc Zyngier , Sean Christopherson , linux-coco@lists.linux.dev, Dylan Reid , abrestic@rivosinc.com, Samuel Ortiz , Christoph Hellwig , Conor Dooley , Greg Kroah-Hartman , Guo Ren , Heiko Stuebner , Jiri Slaby , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, Mayuresh Chitale , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Uladzislau Rezki Subject: [RFC 22/48] RISC-V: KVM: Implement vcpu load/put functions for CoVE guests Date: Wed, 19 Apr 2023 15:16:50 -0700 Message-Id: <20230419221716.3603068-23-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230419221716.3603068-1-atishp@rivosinc.com> References: <20230419221716.3603068-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230419_231818_674321_26A65EDF X-CRM114-Status: GOOD ( 12.62 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The TSM takes care of most of the H extension CSR/fp save/restore for any guest running in CoVE. It may choose to do the fp save/restore lazily as well. The host has to do minimal operations such timer save/restore and interrupt state restore during vcpu load/put. Signed-off-by: Rajnesh Kanwal Signed-off-by: Atish Patra --- arch/riscv/kvm/cove.c | 12 ++++++++++-- arch/riscv/kvm/vcpu.c | 12 +++++++++++- 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kvm/cove.c b/arch/riscv/kvm/cove.c index 87fa04b..c93de9b 100644 --- a/arch/riscv/kvm/cove.c +++ b/arch/riscv/kvm/cove.c @@ -139,12 +139,20 @@ __always_inline bool kvm_riscv_cove_enabled(void) void kvm_riscv_cove_vcpu_load(struct kvm_vcpu *vcpu) { - /* TODO */ + kvm_riscv_vcpu_timer_restore(vcpu); } void kvm_riscv_cove_vcpu_put(struct kvm_vcpu *vcpu) { - /* TODO */ + void *nshmem; + struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; + + kvm_riscv_vcpu_timer_save(vcpu); + /* NACL is mandatory for CoVE */ + nshmem = nacl_shmem(); + + /* Only VSIE needs to be read to manage the interrupt stuff */ + csr->vsie = nacl_shmem_csr_read(nshmem, CSR_VSIE); } int kvm_riscv_cove_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run) diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 8cf462c..3e04b78 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -972,6 +972,11 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) u64 henvcfg = kvm_riscv_vcpu_get_henvcfg(vcpu->arch.isa); struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; + if (is_cove_vcpu(vcpu)) { + kvm_riscv_cove_vcpu_load(vcpu); + goto skip_load; + } + if (kvm_riscv_nacl_sync_csr_available()) { nshmem = nacl_shmem(); nacl_shmem_csr_write(nshmem, CSR_VSSTATUS, csr->vsstatus); @@ -1010,9 +1015,9 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) kvm_riscv_vcpu_host_fp_save(&vcpu->arch.host_context); kvm_riscv_vcpu_guest_fp_restore(&vcpu->arch.guest_context, vcpu->arch.isa); - kvm_riscv_vcpu_aia_load(vcpu, cpu); +skip_load: vcpu->cpu = cpu; } @@ -1023,6 +1028,11 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) vcpu->cpu = -1; + if (is_cove_vcpu(vcpu)) { + kvm_riscv_cove_vcpu_put(vcpu); + return; + } + kvm_riscv_vcpu_aia_put(vcpu); kvm_riscv_vcpu_guest_fp_save(&vcpu->arch.guest_context,