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Wed, 19 Apr 2023 15:18:35 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id jn11-20020a170903050b00b00196807b5189sm11619190plb.292.2023.04.19.15.18.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 15:18:35 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Alexandre Ghiti , Andrew Jones , Andrew Morton , Anup Patel , Atish Patra , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Suzuki K Poulose , Will Deacon , Marc Zyngier , Sean Christopherson , linux-coco@lists.linux.dev, Dylan Reid , abrestic@rivosinc.com, Samuel Ortiz , Christoph Hellwig , Conor Dooley , Greg Kroah-Hartman , Guo Ren , Heiko Stuebner , Jiri Slaby , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, Mayuresh Chitale , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Rajnesh Kanwal , Uladzislau Rezki Subject: [RFC 30/48] RISC-V: KVM: Perform limited operations in hardware enable/disable Date: Wed, 19 Apr 2023 15:16:58 -0700 Message-Id: <20230419221716.3603068-31-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230419221716.3603068-1-atishp@rivosinc.com> References: <20230419221716.3603068-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230419_151839_342521_E415E331 X-CRM114-Status: GOOD ( 14.79 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hardware enable/disable path only need to perform AIA/NACL enable/disable for TVMs. All other operations i.e. interrupt/exception delegation, counter access must be provided by the TSM as host doesn't have control of these operations for a TVM. Signed-off-by: Atish Patra --- arch/riscv/kvm/main.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c index 45ee62d..842b78d 100644 --- a/arch/riscv/kvm/main.c +++ b/arch/riscv/kvm/main.c @@ -13,6 +13,7 @@ #include #include #include +#include long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) @@ -29,6 +30,15 @@ int kvm_arch_hardware_enable(void) if (rc) return rc; + /* + * We just need to invoke aia enable for CoVE if host is in VS mode + * However, if the host is running in HS mode, we need to initialize + * other CSRs as well for legacy VMs. + * TODO: Handle host in HS mode use case. + */ + if (unlikely(kvm_riscv_cove_enabled())) + goto enable_aia; + hedeleg = 0; hedeleg |= (1UL << EXC_INST_MISALIGNED); hedeleg |= (1UL << EXC_BREAKPOINT); @@ -49,6 +59,7 @@ int kvm_arch_hardware_enable(void) csr_write(CSR_HVIP, 0); +enable_aia: kvm_riscv_aia_enable(); return 0; @@ -58,6 +69,8 @@ void kvm_arch_hardware_disable(void) { kvm_riscv_aia_disable(); + if (unlikely(kvm_riscv_cove_enabled())) + goto disable_nacl; /* * After clearing the hideleg CSR, the host kernel will receive * spurious interrupts if hvip CSR has pending interrupts and the @@ -69,6 +82,7 @@ void kvm_arch_hardware_disable(void) csr_write(CSR_HEDELEG, 0); csr_write(CSR_HIDELEG, 0); +disable_nacl: kvm_riscv_nacl_disable(); }