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Wed, 19 Apr 2023 15:18:45 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id jn11-20020a170903050b00b00196807b5189sm11619190plb.292.2023.04.19.15.18.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 15:18:44 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Alexandre Ghiti , Andrew Jones , Andrew Morton , Anup Patel , Atish Patra , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Suzuki K Poulose , Will Deacon , Marc Zyngier , Sean Christopherson , linux-coco@lists.linux.dev, Dylan Reid , abrestic@rivosinc.com, Samuel Ortiz , Christoph Hellwig , Conor Dooley , Greg Kroah-Hartman , Guo Ren , Heiko Stuebner , Jiri Slaby , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, Mayuresh Chitale , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Rajnesh Kanwal , Uladzislau Rezki Subject: [RFC 34/48] RISC-V: KVM: Initialize CoVE Date: Wed, 19 Apr 2023 15:17:02 -0700 Message-Id: <20230419221716.3603068-35-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230419221716.3603068-1-atishp@rivosinc.com> References: <20230419221716.3603068-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230419_151845_656506_96A38FF3 X-CRM114-Status: GOOD ( 14.60 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org CoVE initialization depends on few underlying conditions that differs from normal VMs. 1. RFENCE extension is no longer mandatory as TEEH APIs has its own set of fence APIs. 2. SBI NACL is mandatory for TEE VMs to share memory between the host and the TSM. Signed-off-by: Atish Patra --- arch/riscv/kvm/main.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c index 842b78d..a059414 100644 --- a/arch/riscv/kvm/main.c +++ b/arch/riscv/kvm/main.c @@ -102,15 +102,12 @@ static int __init riscv_kvm_init(void) return -ENODEV; } - if (sbi_probe_extension(SBI_EXT_RFENCE) <= 0) { - kvm_info("require SBI RFENCE extension\n"); - return -ENODEV; - } - rc = kvm_riscv_nacl_init(); if (rc && rc != -ENODEV) return rc; + kvm_riscv_cove_init(); + kvm_riscv_gstage_mode_detect(); kvm_riscv_gstage_vmid_detect(); @@ -121,6 +118,15 @@ static int __init riscv_kvm_init(void) return rc; } + /* TVM don't need RFENCE extension as hardware imsic support is mandatory for TVMs + * TODO: This check should happen later if HW_ACCEL mode is not set as RFENCE + * should only be mandatory in that case. + */ + if (!kvm_riscv_cove_enabled() && sbi_probe_extension(SBI_EXT_RFENCE) <= 0) { + kvm_info("require SBI RFENCE extension\n"); + return -ENODEV; + } + kvm_info("hypervisor extension available\n"); if (kvm_riscv_nacl_available()) {