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Wed, 19 Apr 2023 15:18:53 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id jn11-20020a170903050b00b00196807b5189sm11619190plb.292.2023.04.19.15.18.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 15:18:53 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Rajnesh Kanwal , Atish Patra , Alexandre Ghiti , Andrew Jones , Andrew Morton , Anup Patel , Atish Patra , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Suzuki K Poulose , Will Deacon , Marc Zyngier , Sean Christopherson , linux-coco@lists.linux.dev, Dylan Reid , abrestic@rivosinc.com, Samuel Ortiz , Christoph Hellwig , Conor Dooley , Greg Kroah-Hartman , Guo Ren , Heiko Stuebner , Jiri Slaby , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, Mayuresh Chitale , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Uladzislau Rezki Subject: [RFC 38/48] RISC-V: Add CoVE guest config and helper functions Date: Wed, 19 Apr 2023 15:17:06 -0700 Message-Id: <20230419221716.3603068-39-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230419221716.3603068-1-atishp@rivosinc.com> References: <20230419221716.3603068-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230419_231854_640823_883ABCA7 X-CRM114-Status: GOOD ( 19.30 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Rajnesh Kanwal Introduce a separate config for the guest running in CoVE so that it can be enabled separately if required. However, the default config will enable both CoVE host & guest configs in order to make single image work as both host & guest. Introduce a helper function to detect if a guest is TVM or not at run time. The TSM only enables the CoVE guest SBI extension for TVMs. Signed-off-by: Rajnesh Kanwal Co-developed-by: Atish Patra Signed-off-by: Atish Patra --- arch/riscv/Kbuild | 2 ++ arch/riscv/Kconfig | 6 ++++++ arch/riscv/cove/Makefile | 2 ++ arch/riscv/cove/core.c | 28 ++++++++++++++++++++++++++++ arch/riscv/include/asm/cove.h | 27 +++++++++++++++++++++++++++ arch/riscv/kernel/setup.c | 2 ++ 6 files changed, 67 insertions(+) create mode 100644 arch/riscv/cove/Makefile create mode 100644 arch/riscv/cove/core.c create mode 100644 arch/riscv/include/asm/cove.h diff --git a/arch/riscv/Kbuild b/arch/riscv/Kbuild index afa83e3..ecd661e 100644 --- a/arch/riscv/Kbuild +++ b/arch/riscv/Kbuild @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_RISCV_COVE_GUEST) += cove/ + obj-y += kernel/ mm/ net/ obj-$(CONFIG_BUILTIN_DTB) += boot/dts/ obj-y += errata/ diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 8462941..49c3006 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -512,6 +512,12 @@ config RISCV_COVE_HOST That means the platform should be capable of running TEE VM (TVM) using KVM and TEE Security Manager (TSM). +config RISCV_COVE_GUEST + bool "Guest Support for Confidential VM Extension(CoVE)" + default n + help + Enables support for running TVMs on platforms supporting CoVE. + endmenu # "Confidential VM Extension(CoVE) Support" endmenu # "Platform type" diff --git a/arch/riscv/cove/Makefile b/arch/riscv/cove/Makefile new file mode 100644 index 0000000..03a0cac --- /dev/null +++ b/arch/riscv/cove/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_RISCV_COVE_GUEST) += core.o diff --git a/arch/riscv/cove/core.c b/arch/riscv/cove/core.c new file mode 100644 index 0000000..7218fe7 --- /dev/null +++ b/arch/riscv/cove/core.c @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Confidential Computing Platform Capability checks + * + * Copyright (c) 2023 Rivos Inc. + * + * Authors: + * Rajnesh Kanwal + */ + +#include +#include +#include +#include + +static bool is_tvm; + +bool is_cove_guest(void) +{ + return is_tvm; +} +EXPORT_SYMBOL_GPL(is_cove_guest); + +void riscv_cove_sbi_init(void) +{ + if (sbi_probe_extension(SBI_EXT_COVG) > 0) + is_tvm = true; +} diff --git a/arch/riscv/include/asm/cove.h b/arch/riscv/include/asm/cove.h new file mode 100644 index 0000000..c4d609d --- /dev/null +++ b/arch/riscv/include/asm/cove.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * TVM helper functions + * + * Copyright (c) 2023 Rivos Inc. + * + * Authors: + * Rajnesh Kanwal + */ + +#ifndef __RISCV_COVE_H__ +#define __RISCV_COVE_H__ + +#ifdef CONFIG_RISCV_COVE_GUEST +void riscv_cove_sbi_init(void); +bool is_cove_guest(void); +#else /* CONFIG_RISCV_COVE_GUEST */ +static inline bool is_cove_guest(void) +{ + return false; +} +static inline void riscv_cove_sbi_init(void) +{ +} +#endif /* CONFIG_RISCV_COVE_GUEST */ + +#endif /* __RISCV_COVE_H__ */ diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 7b2b065..20b0280 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -35,6 +35,7 @@ #include #include #include +#include #include "head.h" @@ -272,6 +273,7 @@ void __init setup_arch(char **cmdline_p) early_ioremap_setup(); sbi_init(); + riscv_cove_sbi_init(); jump_label_init(); parse_early_param();