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Wed, 19 Apr 2023 15:18:56 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id jn11-20020a170903050b00b00196807b5189sm11619190plb.292.2023.04.19.15.18.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 15:18:55 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Rajnesh Kanwal , Atish Patra , Alexandre Ghiti , Andrew Jones , Andrew Morton , Anup Patel , Atish Patra , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Suzuki K Poulose , Will Deacon , Marc Zyngier , Sean Christopherson , linux-coco@lists.linux.dev, Dylan Reid , abrestic@rivosinc.com, Samuel Ortiz , Christoph Hellwig , Conor Dooley , Greg Kroah-Hartman , Guo Ren , Heiko Stuebner , Jiri Slaby , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, Mayuresh Chitale , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Uladzislau Rezki Subject: [RFC 39/48] RISC-V: Implement COVG SBI extension Date: Wed, 19 Apr 2023 15:17:07 -0700 Message-Id: <20230419221716.3603068-40-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230419221716.3603068-1-atishp@rivosinc.com> References: <20230419221716.3603068-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230419_151856_731413_0C8C36A5 X-CRM114-Status: GOOD ( 17.10 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Rajnesh Kanwal COVG extension defines the guest side interface for running a guest in CoVE. These functions allow a CoVE guest to share/unshare memory, ask host to trap and emulate MMIO regions and allow/deny injection of interrupts from host. Signed-off-by: Rajnesh Kanwal Signed-off-by: Atish Patra --- arch/riscv/cove/Makefile | 2 +- arch/riscv/cove/cove_guest_sbi.c | 109 ++++++++++++++++++++++++++++++ arch/riscv/include/asm/covg_sbi.h | 38 +++++++++++ 3 files changed, 148 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/cove/cove_guest_sbi.c create mode 100644 arch/riscv/include/asm/covg_sbi.h diff --git a/arch/riscv/cove/Makefile b/arch/riscv/cove/Makefile index 03a0cac..a95043b 100644 --- a/arch/riscv/cove/Makefile +++ b/arch/riscv/cove/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_RISCV_COVE_GUEST) += core.o +obj-$(CONFIG_RISCV_COVE_GUEST) += core.o cove_guest_sbi.o diff --git a/arch/riscv/cove/cove_guest_sbi.c b/arch/riscv/cove/cove_guest_sbi.c new file mode 100644 index 0000000..af22d5e --- /dev/null +++ b/arch/riscv/cove/cove_guest_sbi.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * COVG SBI extensions related helper functions. + * + * Copyright (c) 2023 Rivos Inc. + * + * Authors: + * Rajnesh Kanwal + */ + +#include +#include +#include + +int sbi_covg_add_mmio_region(unsigned long addr, unsigned long len) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_COVG, SBI_EXT_COVG_ADD_MMIO_REGION, addr, len, + 0, 0, 0, 0); + if (ret.error) + return sbi_err_map_linux_errno(ret.error); + + return 0; +} + +int sbi_covg_remove_mmio_region(unsigned long addr, unsigned long len) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_COVG, SBI_EXT_COVG_REMOVE_MMIO_REGION, addr, + len, 0, 0, 0, 0); + if (ret.error) + return sbi_err_map_linux_errno(ret.error); + + return 0; +} + +int sbi_covg_share_memory(unsigned long addr, unsigned long len) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_COVG, SBI_EXT_COVG_SHARE_MEMORY, addr, len, 0, + 0, 0, 0); + if (ret.error) + return sbi_err_map_linux_errno(ret.error); + + return 0; +} + +int sbi_covg_unshare_memory(unsigned long addr, unsigned long len) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_COVG, SBI_EXT_COVG_UNSHARE_MEMORY, addr, len, 0, + 0, 0, 0); + if (ret.error) + return sbi_err_map_linux_errno(ret.error); + + return 0; +} + +int sbi_covg_allow_external_interrupt(unsigned long id) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_COVG, SBI_EXT_COVG_ALLOW_EXT_INTERRUPT, id, 0, + 0, 0, 0, 0); + if (ret.error) + return sbi_err_map_linux_errno(ret.error); + + return 0; +} + +int sbi_covg_allow_all_external_interrupt(void) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_COVG, SBI_EXT_COVG_ALLOW_EXT_INTERRUPT, -1, 0, + 0, 0, 0, 0); + if (ret.error) + return sbi_err_map_linux_errno(ret.error); + + return 0; +} + +int sbi_covg_deny_external_interrupt(unsigned long id) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_COVG, SBI_EXT_COVG_DENY_EXT_INTERRUPT, id, 0, 0, + 0, 0, 0); + if (ret.error) + return sbi_err_map_linux_errno(ret.error); + + return 0; +} + +int sbi_covg_deny_all_external_interrupt(void) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_COVG, SBI_EXT_COVG_DENY_EXT_INTERRUPT, -1, 0, 0, + 0, 0, 0); + if (ret.error) + return sbi_err_map_linux_errno(ret.error); + + return 0; +} diff --git a/arch/riscv/include/asm/covg_sbi.h b/arch/riscv/include/asm/covg_sbi.h new file mode 100644 index 0000000..31283de --- /dev/null +++ b/arch/riscv/include/asm/covg_sbi.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * COVG SBI extension related header file. + * + * Copyright (c) 2023 Rivos Inc. + * + * Authors: + * Rajnesh Kanwal + */ + +#ifndef __RISCV_COVG_SBI_H__ +#define __RISCV_COVG_SBI_H__ + +#ifdef CONFIG_RISCV_COVE_GUEST + +int sbi_covg_add_mmio_region(unsigned long addr, unsigned long len); +int sbi_covg_remove_mmio_region(unsigned long addr, unsigned long len); +int sbi_covg_share_memory(unsigned long addr, unsigned long len); +int sbi_covg_unshare_memory(unsigned long addr, unsigned long len); +int sbi_covg_allow_external_interrupt(unsigned long id); +int sbi_covg_allow_all_external_interrupt(void); +int sbi_covg_deny_external_interrupt(unsigned long id); +int sbi_covg_deny_all_external_interrupt(void); + +#else + +static inline int sbi_covg_add_mmio_region(unsigned long addr, unsigned long len) { return 0; } +static inline int sbi_covg_remove_mmio_region(unsigned long addr, unsigned long len) { return 0; } +static inline int sbi_covg_share_memory(unsigned long addr, unsigned long len) { return 0; } +static inline int sbi_covg_unshare_memory(unsigned long addr, unsigned long len) { return 0; } +static inline int sbi_covg_allow_external_interrupt(unsigned long id) { return 0; } +static inline int sbi_covg_allow_all_external_interrupt(void) { return 0; } +static inline int sbi_covg_deny_external_interrupt(unsigned long id) { return 0; } +static inline int sbi_covg_deny_all_external_interrupt(void) { return 0; } + +#endif + +#endif /* __RISCV_COVG_SBI_H__ */