diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 3d2934b15e80..446801fb7495 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -23,6 +23,9 @@ description: |
   two cores, each of which has two hyperthreads, could be described as
   having four harts.
 
+allOf:
+  - $ref: extensions.yaml
+
 properties:
   compatible:
     oneOf:
@@ -79,25 +82,6 @@ properties:
     description:
       The blocksize in bytes for the Zicboz cache operations.
 
-  riscv,isa:
-    description:
-      Identifies the specific RISC-V instruction set architecture
-      supported by the hart.  These are documented in the RISC-V
-      User-Level ISA document, available from
-      https://riscv.org/specifications/
-
-      Due to revisions of the ISA specification, some deviations
-      have arisen over time.
-      Notably, riscv,isa was defined prior to the creation of the
-      Zicsr and Zifencei extensions and thus "i" implies
-      "zicsr_zifencei".
-
-      While the isa strings in ISA specification are case
-      insensitive, letters in the riscv,isa string must be all
-      lowercase to simplify parsing.
-    $ref: "/schemas/types.yaml#/definitions/string"
-    pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
-
   # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
   timebase-frequency: false
 
@@ -133,8 +117,13 @@ properties:
       DMIPS/MHz, relative to highest capacity-dmips-mhz
       in the system.
 
+oneOf:
+  - required:
+      - riscv,isa
+  - required:
+      - riscv,isa-base
+
 required:
-  - riscv,isa
   - interrupt-controller
 
 additionalProperties: true
@@ -177,7 +166,13 @@ examples:
                 i-tlb-size = <32>;
                 mmu-type = "riscv,sv39";
                 reg = <1>;
-                riscv,isa = "rv64imafdc";
+                riscv,isa-base = "rv64i";
+                riscv,isa-extension-i;
+                riscv,isa-extension-m;
+                riscv,isa-extension-a;
+                riscv,isa-extension-f;
+                riscv,isa-extension-d;
+                riscv,isa-extension-c;
                 tlb-split;
                 cpu_intc1: interrupt-controller {
                         #interrupt-cells = <1>;
@@ -196,7 +191,13 @@ examples:
                 device_type = "cpu";
                 reg = <0>;
                 compatible = "riscv";
-                riscv,isa = "rv64imafdc";
+                riscv,isa-base = "rv64i";
+                riscv,isa-extension-i;
+                riscv,isa-extension-m;
+                riscv,isa-extension-a;
+                riscv,isa-extension-f;
+                riscv,isa-extension-d;
+                riscv,isa-extension-c;
                 mmu-type = "riscv,sv48";
                 interrupt-controller {
                         #interrupt-cells = <1>;
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
new file mode 100644
index 000000000000..1b4d726f7174
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -0,0 +1,259 @@
+# SPDX-License-Identifier: (GPL-2.0 OR MIT)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/extensions.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V ISA extensions
+
+maintainers:
+  - Paul Walmsley <paul.walmsley@sifive.com>
+  - Palmer Dabbelt <palmer@sifive.com>
+  - Conor Dooley <conor@kernel.org>
+
+description: |
+  RISC-V has large number of extensions, some of which "standard" extensions,
+  meaning they are ratified by RISC-V International, and others are "vendor"
+  extensions.  This document defines properties that indicate whether a hart
+  supports a given extensions.
+
+  Once a standard extension has been ratified, no features can be added or
+  removed without the creation of a new extension for that sub- or super-set.
+  The properties for standard extensions therefore map to their originally
+  ratified states, with the exception of the I, Zicntr & Zihpm extensions.
+
+select:
+  properties:
+    compatible:
+      contains:
+        const: riscv
+
+properties:
+  riscv,isa:
+    description:
+      Identifies the specific RISC-V instruction set architecture
+      supported by the hart.  These are documented in the RISC-V
+      User-Level ISA document, available from
+      https://riscv.org/specifications/
+
+      Due to revisions of the ISA specification, some deviations
+      have arisen over time.
+      Notably, riscv,isa was defined prior to the creation of the
+      Zicsr and Zifencei extensions and thus "i" implies
+      "zicsr_zifencei".
+
+      While the isa strings in ISA specification are case
+      insensitive, letters in the riscv,isa string must be all
+      lowercase to simplify parsing.
+
+      This property has been deprecated due to disparity between the
+      extension at the time of its creation and ratification of the
+      base ISA.
+
+    $ref: /schemas/types.yaml#/definitions/string
+    pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
+    deprecated: true
+
+  riscv,isa-base:
+    description:
+      The base ISA implemented by this hart, as described by the 20191213
+      version of the unprivileged ISA specification.
+    enum:
+      - rv32i
+      - rv64i
+
+  riscv,isa-extension-i:
+    type: boolean
+    description:
+      The base integer instruction set, as ratified in the 20191213 version of the
+      unprivileged ISA specification.
+
+  riscv,isa-extension-m:
+    type: boolean
+    description:
+      The standard M extension for integer multiplication and division, as
+      ratified in the 20191213 version of the unprivileged ISA specification.
+
+  riscv,isa-extension-a:
+    type: boolean
+    description:
+      The standard A extension for atomic instructions, as ratified in the
+      20191213 version of the unprivileged ISA specification.
+
+  riscv,isa-extension-f:
+    type: boolean
+    description:
+      The standard M extension for single-precision floating point, as
+      ratified in the 20191213 version of the unprivileged ISA specification.
+
+  riscv,isa-extension-d:
+    type: boolean
+    description:
+      The standard M extension for double-precision floating-point, as
+      ratified in the 20191213 version of the unprivileged ISA specification.
+
+  riscv,isa-extension-q:
+    type: boolean
+    description:
+      The standard M extension for quad-precision floating-point, as ratified in
+      the 20191213 version of the unprivileged ISA specification.
+
+  riscv,isa-extension-c:
+    type: boolean
+    description:
+      The standard M extension for compressed instructions, as ratified in the
+      20191213 version of the unprivileged ISA specification.
+
+  riscv,isa-extension-v:
+    type: boolean
+    description:
+      The standard V extension for vector operations, as ratified in-and-around
+      commit 7a6c8ae ("Fix text that describes vfmv.v.f encoding") of the
+      riscv-v-spec.
+
+  riscv,isa-extension-h:
+    type: boolean
+    description:
+      The standard h extension for hypervisors as ratified in the 20191213
+      version of the privileged ISA specification.
+
+  # Additional Standard Extensions, sorted by category then alphabetically
+
+  riscv,isa-extension-zicntr:
+    type: boolean
+    description:
+      The standard Zicntr extension for base counters and timers, as ratified
+      in the 20191213 version of the unprivileged ISA specification.
+
+  riscv,isa-extension-zicsr:
+    type: boolean
+    description:
+      The standard Zicsr extension for control and status register instructions,
+      as ratified in the 20191213 version of the unprivileged ISA specification.
+
+  riscv,isa-extension-zifencei:
+    type: boolean
+    description:
+      The standard Zifencei extension for instruction-fetch fence, as ratified
+      in the 20191213 version of the unprivileged ISA specification.
+
+  riscv,isa-extension-zihpm:
+    type: boolean
+    description:
+      The standard Zihpm extension for hardware performance counters, as
+      ratified in the 20191213 version of the unprivileged ISA specification.
+
+  riscv,isa-extension-zicbom:
+    type: boolean
+    description:
+      The standard Zicbom extension for base cache management operations as
+      ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
+
+  riscv,isa-extension-zicbop:
+    type: boolean
+    description:
+      The standard Zicbop extension for cache-block prefetch instructions as
+      ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
+
+  riscv,isa-extension-zicboz:
+    type: boolean
+    description:
+      The standard  Zicbomz extension for cache-block zeroing as ratified in
+      commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
+
+  riscv,isa-extension-zihintpause:
+    type: boolean
+    description: |
+      The standard Zihintpause extension for pause hints, as ratified in
+      commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
+
+  riscv,isa-extension-zba:
+    type: boolean
+    description: |
+      The standard Zba bit-manipulation extension for address generation
+      acceleration instructions as ratified at commit 6d33919 ("Merge pull
+      request #158 from hirooih/clmul-fix-loop-end-condition") of
+      riscv-bitmanip.
+
+  riscv,isa-extension-zbb:
+    type: boolean
+    description: |
+      The standard Zbb bit-manipulation extension for basic bit-manipulation as
+      atified at commit 6d33919 ("Merge pull request #158 from
+      hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
+
+  riscv,isa-extension-zbc:
+    type: boolean
+    description: |
+      The standard Zbc bit-manipulation extension for carry-less multiplication
+      as ratified at commit 6d33919 ("Merge pull request #158 from
+      hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
+
+  riscv,isa-extension-zbs:
+    type: boolean
+    description: |
+      The standard Zbs bit-manipulation extension for single-bit instructions
+      as ratified at commit 6d33919 ("Merge pull request #158 from
+      hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
+
+  riscv,isa-extension-ztso:
+    type: boolean
+    description:
+      The standard Ztso extension for total store ordering, as ratified in
+      commit 2e5236 ("Ztso is now ratified.") of the riscv-isa-manual.
+
+ # Standard Supervisor-level Extensions, sorted by category then alphabetically
+
+  'riscv,isa-extension-smaia':
+    type: boolean
+    description: |
+      The standard Smaia supervisor-level extension for the advanced interrupt
+      architecture for machine-mode-visible csr and behavioural changes to
+      interrupts as frozen at commit ccbddab ("Merge pull request #42 from
+      riscv/jhauser-2023-RC4") of riscv-aia.
+
+  riscv,isa-extension-ssaia:
+    type: boolean
+    description: |
+      The standard Ssaia supervisor-level extension for the advanced interrupt
+      architecture for supervisor-mode-visible csr and behavioural changes to
+      interrupts as frozen at commit ccbddab ("Merge pull request #42 from
+      riscv/jhauser-2023-RC4") of riscv-aia.
+
+  riscv,isa-extension-sscofpmf:
+    type: boolean
+    description: |
+      The standard supervisor-level extension for count overflow and mode-based
+      filtering as ratified at commit 01d1df0 ("Add ability to manually trigger
+      workflow. (#2)") of riscv-count-overflow.
+
+  riscv,isa-extension-sstc:
+    type: boolean
+    description:
+      The standard supervisor-level extension for time compare
+      as ratified at commit 3f9ed34 ("Add ability to manually trigger
+      workflow. (#2)") of riscv-time-compare.
+
+  riscv,isa-extension-svinval:
+    type: boolean
+    description:
+      The standard Svinval supervisor-level extension for fine-grained
+      address-translation cache invalidation as ratified in the 20191213 version
+      of the privileged ISA specification.
+
+  riscv,isa-extension-svnapot:
+    type: boolean
+    description:
+      The standard Svnapot supervisor-level extensions for napot translation
+      contiguity as ratified in the 20191213 version of the privileged ISA
+      specification.
+
+  riscv,isa-extension-svpbmt:
+    type: boolean
+    description:
+      The standard Svpbmt supervisor-level extensions for page-based memory
+      types as ratified in the 20191213 version of the privileged ISA
+      specification.
+
+additionalProperties: true
+...
